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Renesas Electronics Components Datasheet

ICS9250-50 Datasheet

Frequency Generator & Integrated Buffer

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Integrated
Circuit
Systems, Inc.
ICS9250-50
Frequency Generator & Integrated Buffers for PIII & Tualatin™
Recommended Application:
815B Solano B step style chipset
Output Features:
VDDA
• 2 - CPUs @ 2.5V, up to 133MHz.
• 13 - SDRAM @ 3.3V, up to 133MHz.
X1
X2
GNDA
• 3 - 3V66 @ 3.3V, 2x PCI MHz.
• 8 - PCI @ 3.3V
GND3V66
3V66-0
3V66-1
• 1 - 48MHz, @ 3.3V fixed
• 1 - 24/48MHz @ 3.3V
• 1 - REF @ 3.3V, 14.318MHz.
• 1 - IOAPIC @ 2.5V 16.67MHz.
3V66-2
VDD3V66
VDDPCI
1*FS0/PCICLK0
1*FS1/PCICLK1
1*SEL24_48#/PCICLK2
Features:
• Support PC133 SDRAM.
GNDPCI
PCICLK3
PCICLK4
• Up to 133MHz frequency support
• Support power management through PD#
PCICLK5
VDDPCI
PCICLK6
• Spread spectrum for EMI control
(± 0.25% Center Spread or 0 to -0.5% down spread)
• Uses external 14.318MHz crystal
PCICLK7
GNDPCI
Vtt_PWRGD/PD#
SCLK
• FS pins for frequency select
Key Specifications:
SDATA
VDDSDR
SDRAM11
• CPU Output Jitter: <250ps
SDRAM10
GNDSDR
• CPU Output Skew: <175ps
Pin Configuration
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
REF0/FS4*1
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
24_48MHz/FS21*
48MHz/FS3*1
VDD48
VDDSDR
SDRAM8
SDRAM9
GNDSDR
• PCI Output Skew: <500ps
• 3V66 Output Skew <175ps
• For group skew timing, please refer to the
Group Timing Relationship Table.
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
X1
XTAL
X2
OSC
PLL1
Spread
Spectrum
FS(4:0)
PD#
Vtt_PWRGD
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
0594B—09/14/05
/2
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
48MHz
24_48MHz
REF0
2 CPUCLK (1:0)
Functionality
FS4 FS3 FS2 FS1 FS0 CPU SDRAM
0 0 0 0 0 66.67 100.00
0 1 0 0 0 100.00 100.00
1 0 0 0 0 133.33 133.33
1 1 0 0 0 133.33 100.00
3V66
66.67
66.67
66.67
66.67
PCI
33.33
33.33
33.33
33.33
For other hardware/I2C selectable frequencies please
refer to Byte 0 frequency select register.
12 SDRAM (11:0)
SDRAM_F
IOAPIC
PCICLK (7:0)
8
Power Groups
VDD48 = Fixed PLL power
GND48 = Fixed PLL GND
VDDA = Power for CPU PLL
GNDA = GND for CPU PLL
3V66 (2:0)
3


Renesas Electronics Components Datasheet

ICS9250-50 Datasheet

Frequency Generator & Integrated Buffer

No Preview Available !

ICS9250-50
General Description
The ICS9250-50 is a single chip clock solution for desktop designs using the 810/810E, Solano and Solano B- Step
style chipset. It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-
50 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN
NUMBER
PIN NAME TYPE
DESCRIPTION
1
VDDA
PWR 3.3V analog power supply for fixed PLL
9, 10, 18, 25,
32, 33, 37, 45
VDD
2
X1
3
X2
PWR 3.3V power supply
IN
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
OUT Crystal output, nominally 14.318MHz. Has internal load cap (33pF)
4
GNDA
5, 14, 21, 28,
29, 36, 41, 49
GND
8, 7, 6
3V66 (2:0)
11
PCICLK0
FS0
PCICLK1
12
FS1
20, 19, 17,
16, 15
PCICLK (7:3)
PCICLK2
13
SEL24_48#
Vtt_PWRGD
22
PD#
23
SCLK
24
SDATA
48MHz
34
FS3
FS2
35
24_48MHz
38
SDRAM_F
48, 47, 46, 44,
43, 42, 40, 39,
31, 30, 27, 26
SDRAM
(11:0)
50
GNDL
51, 52
CPUCLK (1:0)
53, 55
54
56
VDDL
IOAPIC
FS4
REF0
PWR Analog Ground pin for 3.3V supply for fixed PLL
PWR Ground pins for 3.3V supply
OUT
OUT
IN
OUT
IN
3.3Vclock outputs for HUB @ 2X PCI frequency
3.3V PCI clock outputs
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock outputs.
Logic input frequency select bit. Input latched at power on.
OUT 3.3V PCI clock outputs.
OUT 3.3V PCI clock output.
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
Input logic select. When logic "0" is selected pin 35 = 48MHz
When logic "1" is selected pin 35 = 24MHz.
This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal. When Vtt_PWRGD
goes high the frequency select will be latched at power on thereafter the pin is an asynchronous
active low power down pin.
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power
down will not be greater than 3ms.
Clock input of I2C serial input.
Data input for I2C serial input.
3.3V Fixed 48MHz clock output for USB.
Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
3.3V 24 or 48MHz output.
3.3V free running 100MHz SDRAM not affected by I2C
OUT 3.3V output running 100MHz. All SDRAM outputs can be turned off through I2C.
PWR Ground for 2.5V power supply for CPU & APIC.
OUT 2.5V Host bus clock output. Output frequency derived from FS pins.
PWR
OUT
IN
OUT
2.5V power suypply for CPU, IOAPIC.
2.5V clock outputs running at 16.67MHz.
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
0594B—09/14/05
2


Part Number ICS9250-50
Description Frequency Generator & Integrated Buffer
Maker Renesas
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ICS9250-50 Datasheet PDF






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