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IDT2308B Datasheet

3.3V ZERO DELAY CLOCK BUFFER

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3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
DADTAATSAHSEHEETET
2308B
Description
The 2308B is a high-speed phase-lock loop (PLL) clock
multiplier. It is designed to address high-speed clock
distribution and multiplication applications. The zero delay
is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10
to 133MHz.
The 2308B has two banks of four outputs each that are
controlled via two select addresses. By proper selection of
input addresses, both banks can be put in tri-state mode. In
test mode, the PLL is turned off, and the input clock directly
drives the outputs for system testing purposes. In the
absence of an input clock, the 2308B enters power down,
and the outputs are tri-stated. In this mode, the device will
draw less than 25µA.
The 2308B is available in six unique configurations for both
prescaling and multiplication of the Input REF Clock. (see
Available Options for 2308B table.)
The PLL is closed externally to provide more flexibility by
allowing the user to control the delay between the input
clock and the outputs.
Features
Phase-Lock Loop Clock Distribution for Applications
ranging from 10MHz to 133MHz operating frequency
Distributes one clock input to two banks of four outputs
Separate output enable for each output bank
External feedback (FBK) pin is used to synchronize the
outputs to the clock input
Output Skew < 200 ps
Low jitter < 200 ps cycle-to-cycle
1x, 2x, 4x output options (see Available Options for
2308B table)
No external RC network required
Operates at 3.3 V VDD
Available in 16-SOIC and 16-TSSOP packages
Available in commercial and industrial temperature
ranges
Block Diagram
©2021 Renesas Electronics Corporation
1
R31DS0037EU0300
MAY 21, 2021


Renesas Electronics Components Datasheet

IDT2308B Datasheet

3.3V ZERO DELAY CLOCK BUFFER

No Preview Available !

2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Applications
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
Function Table1 Select Input Decoding
S2 S1 CLKA
L L Tri-state
L H Driven
H L Driven
H H Driven
CLKB
Tri-state
Tri-state
Driven
Driven
Output
Source
PLL
PLL
REF
PLL
PLL Shut
Down
Y
N
Y
N
Note 1: H = HIGH voltage level; L = LOW voltage level
Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF1
CLKA12
CLKA22
VDD
GND
CLKB12
CLKB22
S23
S13
CLKB32
CLKB42
GND
VDD
CLKA32
CLKA42
FBK
Pin Description
Input Reference Clock, 5 Volt Tolerant Input.
Clock Output for Bank A.
Clock Output for Bank A.
3.3 V Supply.
Ground.
Clock Output for Bank B.
Clock Output for Bank B.
Select Input, Bit 2.
Select Input, Bit 1.
Clock Output for Bank B.
Clock Output for Bank B.
Ground.
3.3 V Supply.
Clock Output for Bank A.
Clock Output for Bank A.
PLL Feedback Input.
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-up on these inputs.
©2021 Renesas Electronics Corporation
2
R31DS0037EU0300
MAY 21, 2021


Part Number IDT2308B
Description 3.3V ZERO DELAY CLOCK BUFFER
Maker Renesas
PDF Download

IDT2308B Datasheet PDF






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