IDT5P30017 Datasheet | Renesas

Low Skew 1 to 2 Clock Buffer Description The IDT5P30017 is a low skew, single input to two output, clock buffer. The device operates from a single 1.8 to 3.3 volt supply and has a 1.8 to 3.3 volt tolerant input, making it ideal for level translation. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs. Features - Low skew outputs (50 ps) - Packaged in 6-pin DFN (1.4 x 1.4mm) - Ro HS (lead-free) pliant package - Low power CMOS technology - Operating voltages of 1.8 V to 3.3 V - Frequency range of operation: 0 to 200MHz - Output Enable pin tri-states outputs - Industrial temperature range Block Diagram ICLK CLK0 CLK1 Output Enable IDT5P30017 REVISION F 12/08/14 ©2014 Integrated Device Technology, Inc. IDT5P30017 DATASHEET Pin Assignment (6-pin DFN) ICLK 1 CLK1 GND 3 6 OE VDD 4 CLK0 Pin Descriptions Pin Pin Number Name 1 ICLK 2 CLK1 3 GND 4 CLK0 5 VDD 6 OE Pin Type Input Output Power Output Power Input Pin Description Clock Input. 1.8 to 3.3 V tolerant input. Clock Output 1. Connect to ground. Clock Output 0. Connect to +1.8 V or +3.3 V. Output Enable with 250kohm internal series resistor. Tri-states outputs when low. External...