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IDT72275 Datasheet CMOS Supersync Fifo

Manufacturer: Renesas

Overview: CMOS SuperSync FIFO™ 32,768 x 18 65,536 x 18 IDT72275 IDT72285 OBSOLETE.

General Description

: • Master Reset clears entire FIFO The IDT72275/72285 are exceptionally deep, high speed, CMOS First-In- • Partial Reset clears data, but retains programmable settings • Retransmit operation with fixed, low first word data T R latency time • Empty, Full and Half-Full flags signal FIFO status R O • Programmable Almost-Empty and Almost-Full flags, each flag F can default to one of two preselected offsets A • Program partial flags by either serial or parallel means P D • Select IDT Standard timing (using EF and FF flags) or First E E Word Fall Through timing (using OR and IR flags) • Output enable puts data outputs into high impedance state T D • Easily expandable in depth and width LE EN NS FUNCTIONAL BLOCK DIAGRAM First-Out (FIFO) memories with clocked read and write controls.

These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas been removed.

The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency.

Key Features

  • Independent Read and Write Clocks (permit reading and writing.
  • Choose among the following memory organizations: IDT72275.
  • 32,768 x 18 IDT72285.
  • 65,536 x 18.
  • Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs.
  • 10ns read/write cycle time (6.5ns access time) simultaneously).
  • Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64- pin Slim Thin Quad Flat Pack (STQFP).
  • High-performance submicron CMOS technolog.

IDT72275 Distributor & Price

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Similar Datasheet

Brand Logo Part Number Description Manufacturer
IDT Logo IDT72275 (IDT72275 / IDT72285) CMOS SUPERSYNC FIFO IDT

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