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IDT72V36110 Datasheet

3.3 VOLT HIGH-DENSITY SUPERSYNC FIFO

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3.3 VOLT HIGH-DENSITY SUPERSYNC II™
36-BIT FIFO
65,536 x 36
IDT72V36100
131,072 x 36
IDT72V36110
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
Choose among the following memory organizations:
IDT72V36100 65,536 x 36
IDT72V36110 131,072 x 36
Higher density, 2Meg and 4Meg SuperSync II FIFOs
Up to 166 MHz Operation of the Clocks
User selectable Asynchronous read and/or write ports (PBGA Only)
User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
Big-Endian/Little-Endian user selectable byte representation
5V input tolerant
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
JTAG port, provided for Boundary Scan function (PBGA Only)
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic
Ball Grid Array (PBGA) (with additional features)
Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/
72V3670/72V3680/72V3690) family
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
*Available on the PBGA package only.
* WEN WCLK/WR
D0 -Dn (x36, x18 or x9)
LD SEN
*ASYW
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
65,536 x 36
131,072 x 36
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
BE
IP
BM
IW
OW
MRS
PRS
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
TCK
*TRST
* TMS
* TDI
**TDO
JTAG CONTROL
(BOUNDARY
SCAN)
*
OE
Q0 -Qn (x36, x18 or x9)
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
© 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RT
RM
* ASYR
* RCLK/RD
REN
6117 drw01
MARCH 2018
DSC-6117/16


Renesas Electronics Components Datasheet

IDT72V36110 Datasheet

3.3 VOLT HIGH-DENSITY SUPERSYNC FIFO

No Preview Available !

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION:
The IDT72V36100/72V36110 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls and a
flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key
user benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
empty FIFO to the time it can be read, is fixed and short.
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 4 Mbit
Bus-Matching Sync FIFOs are particularly appropriate for network, video,
telecommunications, data communications and other applications that need to
buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
PIN CONFIGURATIONS
INDEX
WEN
1
SEN
2
DNC(1)
3
VCC
4
DNC(1)
5
IW
6
D35
7
D34
8
D33
9
D32
10
VCC
11
D31
12
D30
13
GND
14
D29
15
D28
16
D27
17
D26
18
D25
19
D24
20
D23
21
GND
22
D22
23
VCC
24
D21
25
D20
26
D19
27
D18
28
GND
29
D17
30
D16
31
D15
32
D14
33
D13
34
VCC
35
D12
36
GND
37
D11
38
102
OE
101
VCC
100
VCC
99
Q35
98
Q34
97
Q33
96
Q32
95
GND
94
GND
93
Q31
92
Q30
91
Q29
90
Q28
89
Q27
88
Q26
87
VCC
86
Q25
85
Q24
84
GND
83
GND
82
Q23
81
Q22
80
Q21
79
Q20
78
Q19
77
Q18
76
GND
75
Q17
74
Q16
73
VCC
72
VCC
71
Q15
70
Q14
69
Q13
68
Q12
67
GND
66
Q11
65
Q10
NOTE:
1. DNC = Do Not Connect.
TQFP (PK128, PKG128) Order code: PF
TOP VIEW
2
6117 drw02


Part Number IDT72V36110
Description 3.3 VOLT HIGH-DENSITY SUPERSYNC FIFO
Maker Renesas
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IDT72V36110 Datasheet PDF






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