IDT72V3643
Description
The IDT72V3623/72V3643 are pin and functionally patible versions of the IDT723623/723643, designed to run off a 3.3V supply for exceptionally low power consumption.
Key Features
- Clock frequencies up to 100 MHz (6.5 ns access time)
- Clocked FIFO buffering data from Port A to Port B
- IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag functions)
- Programmable Almost-Empty and Almost-Full flags; each has three default offsets (8, 16 and 64)
- Serial or parallel programming of partial flags
- Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)
- Big- or Little-Endian format for word and byte bus sizes
- Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
- Mailbox bypass registers for each FIFO
- Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)
