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Renesas Electronics Components Datasheet

ISLA112P50 Datasheet

500MSPS A/D Converter

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ISLA112P50
12-Bit, 500MSPS A/D Converter
The ISLA112P50 is a low-power, high-performance, 500MSPS
analog-to-digital converter designed with Intersil’s proprietary
FemtoCharge™ technology on a standard CMOS process. The
ISLA112P50 is part of a pin-compatible portfolio of 8, 10 and
12-bit A/Ds. This device an upgrade of the KAD551XP-50
product family and is pin similar.
The device utilizes two time-interleaved 250MSPS unit A/Ds to
achieve the ultimate sample rate of 500MSPS. A single
500MHz conversion clock is presented to the converter, and all
interleave clocking is managed internally. The proprietary
Intersil Interleave Engine (I2E) performs automatic fine
correction of offset, gain, and sample time skew mismatches
between the unit A/Ds to optimize performance. No external
interleaving algorithm is required.
A serial peripheral interface (SPI) port allows for extensive
configurability of the A/D. The SPI also controls the interleave
correction circuitry, allowing the system to issue continuous
calibration commands as well as configure many dynamic
parameters.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA112P50 is available in a 72 Ld QFN package
with an exposed paddle. Performance is specified over the full
industrial temperature range (-40°C to +85°C).
DATASHEET
FN7604
Rev 2.00
August 1, 2011
Features
• 1.15GHz Analog Input Bandwidth
• 90fs Clock Jitter
• Automatic Fine Interleave Correction Calibration
• Multiple Chip Time Alignment Support via the Synchronous
Clock Divider Reset
• Programmable Gain, Offset and Skew Control
• Over-Range Indicator
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Test Patterns and Internal Temperature
Sensor
Applications
• Radar and Electronic/Signal Intelligence
• Broadband Communications
• High-Performance Data Acquisition
Pin-Compatible Family
CLKP
CLKN
CLOCK
MANAGEMENT
CLKOUTP
CLKOUTN
MODEL
ISLA112P50
ISLA110P50
ISLA118P50
RESOLUTION
12
10
8
SPEED
(MSPS)
500
500
500
Key Specifications
SHA
12 - BIT
250 MSPS
ADC
VREF
D[11:0]P
D[11:0]N
ORP
• SNR = 65.8dBFS for fIN = 190MHz (-1dBFS)
• SFDR = 80dBc for fIN = 190MHz (-1dBFS)
VINP
DIGITAL
ORN
• Total Power Consumption = 455mW
VINN
Gain/Offset/Skew
Adjustments
I2 E ERROR
CORRECTION
OUTFMT
VCM
SHA
12 - BIT
250 MSPS
ADC
VREF
1.25V
+
SPI
CONTROL
OUTMODE
FIGURE 1. BLOCK DIAGRAM
FN7604 Rev 2.00
August 1, 2011
Page 1 of 34


Renesas Electronics Components Datasheet

ISLA112P50 Datasheet

500MSPS A/D Converter

No Preview Available !

ISLA112P50
Table of Contents
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 5
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . 10
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Over-Range Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I2E Requirements and Restrictions . . . . . . . . . . . . . . . . . . .18
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Active Run State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Nyquist Zones. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Configurability and Communication . . . . . . . . . . . . . . . . . . . . 19
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . 20
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Indexed Device Configuration/Control. . . . . . . . . . . . . . . . . . 23
AC RMS Power Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Address 0x60-0x64: I2E initialization . . . . . . . . . . . . . . . . . . 25
Device Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
A/D Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . 31
Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Exposed Paddle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LVCMOS Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FN7604 Rev 2.00
August 1, 2011
Page 2 of 34


Part Number ISLA112P50
Description 500MSPS A/D Converter
Maker Renesas
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ISLA112P50 Datasheet PDF






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