ISLA214P13 - 14-Bit ADC

Renesas

Datasheet Details

- 72 Ld QFN, LVDS Mode . . 7 Ord

Single supply 1.8V operation.
Clock duty cycle stabilizer.
75fs clock jitter.
700MHz bandwidth.
Programmable built-in test patterns.
Multi-ADC support - SPI programmable fine gain and offset control - Support for multiple ADC synchronization - Optimized output timing.
Nap and sleep modes - 200µs sleep wake-up time.
Data output clock.
SDR/DDR LVDS-compatible or LVCMOS outputs.
Selectable clock divider Appli.

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Published: May 30, 2020 |