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MK2049-45 - CLOCK PLL

Download the MK2049-45 datasheet PDF. This datasheet also covers the MK2049-45A variant, as both devices belong to the same clock pll family and are provided as variant models within a single manufacturer datasheet.

General Description

The MK2049-45A is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation.

The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter.

The second PLL is a translator for frequency multiplication.

Key Features

  • Packaged in 20-pin SOIC.
  • 3.3 V + 5% operation.
  • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E.
  • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz.
  • Locks to 8 kHz + 100 ppm (External mode).
  • Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs.
  • Exact internal ratios enable zero.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MK2049-45A-Renesas.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
MK2049-45 3.3V Communications Clock PLL Integrated Circuit Systems
MK2049-01 Communications Clock PLL Integrated Circuit Systems
MK2049-02 Communications Clock PLLs Integrated Circuit Systems
MK2049-03 Communications Clock PLLs Integrated Circuit Systems
MK2049-34 3.3 V Communications Clock PLL Integrated Circuit Systems

Other Datasheets by Renesas

Part Number Description
MK2049-45 CLOCK PLL
MK2049-34 CLOCK VCXO PLL
MK2049-36 CLOCK PLL
MK2302-01 MULTIPLIER AND ZERO DELAY BUFFER
MK2304-2 LOW SKEW BUFFER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
3.3 VOLT COMMUNICATIONS CLOCK PLL DATASHEET MK2049-45A Description The MK2049-45A is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication. Basic configuration is determined by a Mode/Frequency Selection Table. Loop bandwidth and damping factor are programmable via external loop filter component selection. Buffer Mode accepts a 10 to 50 MHz input and will provide a jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK. In this mode the MK2049-45A is ideal for filtering jitter from high frequency clocks.