MK2049-45, MK2049-45A - CLOCK PLL

Renesas

Datasheet Details

Part number	MK2049-45, MK2049-45A
Manufacturer	Renesas
File Size	229.39 KB
Description	CLOCK PLL
Datasheet	MK2049-45A-Renesas.pdf
Note	This datasheet PDF includes multiple part numbers: MK2049-45, MK2049-45A. Please refer to the document for exact specifications by model.

The MK2049-45A is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation.

Packaged in 20-pin SOIC.
3.3 V + 5% operation.
Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E.
Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz.
Locks to 8 kHz + 100 ppm (External mode).
Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs.
Exact internal ratios enable zero.

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Published: May 8, 2020 |