MK2049-45
Description
The MK2049-45A is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation.
Key Features
- Packaged in 20-pin SOIC
- 3.3 V + 5% operation
- Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz
- Locks to 8 kHz + 100 ppm (External mode)
- Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs
- Exact internal ratios enable zero ppm error
- Pb (lead) free package
- Determines CLK input/outputs per table on page
- Internal pull-up resistor. Crystal connection. Connect to a MHz crystal as shown in table on page
- Crystal connection. Connect to a MHz crystal as shown in table on page
