MPC962305 - 3.3V Zero Delay Buffer

Product Overview

Renesas

Datasheet Details

Part number	MPC962305
Manufacturer	Renesas
File Size	765.15 KB
Description	3.3V Zero Delay Buffer
Datasheet	MPC962305 Datasheet
Additional preview pages of the MPC962305 datasheet.

Product details

Description

for MPC962309 Pin Signal 1 REF(1) 2 CLKA1(2) 3 CLKA2(2) 4 VDD 5 GND 6 CLKB1(2) 7 CLKB2(2) 8 S2(3) 9 S1(3) 10 CLKB3(2) 11 CLKB4(2) 12 GND 13 VDD 14 CLKA3(2) 15 CLKA4(2) 16 CLKOUT(2) 1. Weak pull-down.2. Weak pull-down on all outputs.3. Weak pull-ups on these inputs.Description Input reference frequency, 5 V-tolerant input Buffered clock output, Bank A Buffered clock output, Bank A 3.3 V supply Ground Buffered clock output, Bank B Buffered clock output, Bank

Features

1:5 LVCMOS zero-delay buffer (MPC962305).
1:9 LVCMOS zero-delay buffer (MPC962309).
Zero input-output propagation delay.
Multiple low-skew outputs.
250 ps max output-output skew.
700 ps max device-device skew.
Supports a clock I/O frequency range of 10 MHz to 133 MHz, compatible with CPU and PCI bus frequencies.
Low jitter, 200 ps max cycle-cycle, and compatible with Pentium® based systems.
Test Mode to bypass PLL.

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Published: Feb 19, 2024 |