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MPC9772 - 3.3V 1:12 LVCMOS PLL Clock Generator

General Description

The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock.

Normal operation of the MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.

Key Features

  • 1:12 PLL Based Low-Voltage Clock Generator.
  • 3.3 V Power Supply.
  • Internal Power-On Reset.
  • Generates Cock Signals Up to 240 MHz.
  • Maximum Output Skew of 250 ps.
  • On-Chip Crystal Oscillator Clock Reference.
  • Two LVCMOS PLL Reference Clock Inputs.
  • External PLL Feedback Supports Zero-Delay Capability.
  • Various Feedback and Output Dividers (See.

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Datasheet Details

Part number MPC9772
Manufacturer Renesas
File Size 435.53 KB
Description 3.3V 1:12 LVCMOS PLL Clock Generator
Datasheet download datasheet MPC9772 Datasheet

Full PDF Text Transcription for MPC9772 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for MPC9772. For precise diagrams, and layout, please refer to the original PDF.

3.3V 1:12 LVCMOS PLL Clock Generator PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 MPC9772 DATA SHEET The MPC9772 is a 3.3 V compatible, 1:12 P...

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R 7, 2016 MPC9772 DATA SHEET The MPC9772 is a 3.3 V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. Features • 1:12 PLL Based Low-Voltage Clock Generator • 3.

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