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MPC9772 Datasheet

3.3V 1:12 LVCMOS PLL Clock Generator

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3.3V 1:12 LVCMOS PLL Clock Generator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
MPC9772
DATA SHEET
The MPC9772 is a 3.3 V compatible, 1:12 PLL based clock generator targeted
for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With output
frequencies up to 240 MHz and output skews less than 250 ps the device meets
the needs of the most demanding clock applications.
Features
• 1:12 PLL Based Low-Voltage Clock Generator
• 3.3 V Power Supply
• Internal Power-On Reset
• Generates Cock Signals Up to 240 MHz
• Maximum Output Skew of 250 ps
• On-Chip Crystal Oscillator Clock Reference
• Two LVCMOS PLL Reference Clock Inputs
• External PLL Feedback Supports Zero-Delay Capability
• Various Feedback and Output Dividers (See Applications Information
Section)
• Supports Up to Three Individual Generated Output Clock Frequencies
• Synchronous Output Clock Stop Circuitry for Each Individual Output for
Power Down Support
• Drives Up to 24 Clock Lines
• Ambient Temperature Range 0C to +70C
• Pin and Function Compatible To the MPC972
• 52-Lead Pb-Free Package
For drop in replacement use 87972DYI-147
MPC9772
3.3 V 1:12 LVCMOS
PLL CLOCK GENERATOR
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 848D-03
Functional Description
The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as
well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1, and 8:3.
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-
tion the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-
binary factor. The MPC9772 also supports the 180phase shift of one of its output banks with respect to the other output banks.
The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of sys-
tem baseline timing signals.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL char-
acteristics do not apply.
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
MPC9772. The MPC9772 has an internal power-on reset.
The MPC9772 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission
lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package.
MPC9772 REVISION 8 3/16/16
1
©2016 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

MPC9772 Datasheet

3.3V 1:12 LVCMOS PLL Clock Generator

No Preview Available !

MPC9772 DATA SHEET
XTAL_IN
XTAL_OUT
CCLK0
CCLK1
CCLK_SEL
REF_SEL
FB_IN
VCO_SEL
PLL_EN
FSEL_A[0:1]
FSEL_B[0:1]
FSEL_C[0:1]
FSEL_FB[0:2]
INV_CLK
STOP_DATA
STOP_CLK
MR/OE
All input resistors have a value of 25k
XTAL 1
VCC 0
0
1
Ref
VCO
PLL
VCC
0 4, 6, 8, 12
2 0
1 4, 6, 8, 10
1 1
2, 4, 6, 8
4, 6, 8, 10
12, 16, 20
SYNC PULSE
FB
VCC
2
2
2
3
VCC
Power-On Reset
Clock Stop
12
Figure 1. Logic Diagram
Bank A
CLK
Stop
Bank B
CLK
Stop
Bank C
CLK
Stop
0
CLK
1
Stop
CLK
Stop
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
QFB
QSYNC
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
VCC
QA2
GND
QA1
VCC
QA0
GND
VCO_SEL
4039 38 37 36 35 34 33 32 31 30 29 28 2726
41
25
42
24
43
23
44
22
45
21
46
MPC9772
20
47
19
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 10 11 12 13
FSEL_FB1
QSYNC
GND
QC0
VCC
QC1
FSEL_C0
FSEL_C1
QC2
VCC
QC3
GND
INV_CLK
REVISION 8 3/16/16
Figure 2. MPC9772 52-Lead Package Pinout (Top View)
2
©2016 Integrated Device Technology, Inc.


Part Number MPC9772
Description 3.3V 1:12 LVCMOS PLL Clock Generator
Maker Renesas
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MPC9772 Datasheet PDF






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