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NP110N055PUG Datasheet

N-CHANNEL POWER MOS FET

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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP110N055PUG
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
The NP110N055PUG is N-channel MOS Field Effect
Transistor designed for high current switching applications.
ORDERING INFORMATION
PART NUMBER
PACKAGE
NP110N055PUG
TO-263 (MP-25ZP)
FEATURES
Channel temperature 175 degree rating
Super low on-state resistance
RDS(on) = 2.4 mMAX. (VGS = 10 V, ID = 55 A)
Low Ciss: Ciss = 17100 pF TYP.
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
55
Gate to Source Voltage (VDS = 0 V)
VGSS
±20
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
ID(DC)
ID(pulse)
±110
±440
Total Power Dissipation (TA = 25°C)
PT1 1.8
Total Power Dissipation (TC = 25°C)
PT2 288
Channel Temperature
Tch 175
Storage Temperature
Tstg 55 to +175
Repetitive Avalanche Current Note2
IAR 66
Repetitive Avalanche Energy Note2
EAR 435
Notes 1. PW 10 µs, Duty Cycle 1%
2. Tch 150°C, VDD = 28 V, RG = 25 , VGS = 20 0 V
V
V
A
A
W
W
°C
°C
A
mJ
(TO-263)
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
0.52
83.3
°C/W
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D16853EJ1V0DS00 (1st edition)
Date Published September 2004 NS CP(K)
Printed in Japan
2004


Renesas Electronics Components Datasheet

NP110N055PUG Datasheet

N-CHANNEL POWER MOS FET

No Preview Available !

NP110N055PUG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS VDS = 55 V, VGS = 0 V
Gate Leakage Current
Gate to Source Threshold Voltage Note
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
IGSS
VGS(th)
| yfs |
RDS(on)
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 µA
VDS = 10 V, ID = 55 A
VGS = 10 V, ID = 55 A
Input Capacitance
Ciss VDS = 25 V
Output Capacitance
Coss
VGS = 0 V
Reverse Transfer Capacitance
Crss f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 28 V, ID = 55 A
Rise Time
tr VGS = 10 V
Turn-off Delay Time
td(off)
RG = 0
Fall Time
tf
Total Gate Charge
QG VDD = 44 V
Gate to Source Charge
QGS
VGS = 10 V
Gate to Drain Charge
Body Diode Forward Voltage Note
QGD
VF(S-D)
ID = 110 A
IF = 110 A, VGS = 0 V
Reverse Recovery Time
trr IF = 110 A, VGS = 0 V
Reverse Recovery Charge
Note Pulsed
Qrr di/dt = 100 A/µs
MIN. TYP. MAX. UNIT
1 µA
±100 nA
2.0 3.0 4.0
V
42 83
S
1.9 2.4 m
17100 25700 pF
1120 1680 pF
725 1310 pF
63 140 ns
201 510 ns
131 270 ns
19 50 ns
251 380 nC
63 nC
81 nC
0.9 1.5
V
58 ns
87 nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25
PG.
VGS = 20 0 V
50
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 µs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off) tf
ton toff
D.U.T.
IG = 2 mA
PG. 50
RL
VDD
2 Data Sheet D16853EJ1V0DS


Part Number NP110N055PUG
Description N-CHANNEL POWER MOS FET
Maker Renesas
Total Page 7 Pages
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