R5F101SJAFB
Features
Ultra-low power consumption technology
- VDD = single power supply voltage of 1.6 to 5.5 V
- HALT mode
- STOP mode
- SNOOZE mode
RL78 CPU core
- CISC architecture with 3-stage pipeline
- Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz operation with high-speed on-chip oscillator) to ultra-low speed (30.5 μs: @ 32.768 k Hz operation with subsystem clock)
- Address space: 1 MB <R>
- General-purpose registers: (8-bit register × 8) × 4 banks
- On-chip RAM: 2 to 32 KB
Code flash memory
- Code flash memory: 16 to 512 KB
- Block size: 1 KB
- Prohibition of block erase and rewriting (security function)
- On-chip debug function
- Self-programming (with boot swap function/flash shield window function)
Data Flash Memory
- Data flash memory: 4 KB to 8 KB
- Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.
- Number of rewrites: 1,000,000 times (TYP.)
- Voltage of rewrites: VDD =...
