R5F10WLF Datasheet | Renesas

Features Ultra-low power consumption technology - VDD = single power supply voltage of 1.6 to 5.5 V which can operate a 1.8 V device at a low voltage - HALT mode - STOP mode - SNOOZE mode RL78 CPU core - CISC architecture with 3-stage pipeline - Minimum instruction execution time: Can be changed from high speed (0.04167 µs: @ 24 MHz operation with high-speed onchip oscillator) to ultra-low speed (30.5 µs: @ 32.768 k Hz operation with subsystem clock) - Address space: 1 MB - General-purpose registers: (8-bit register × 8) × 4 banks - On-chip RAM: 1 to 8 KB Code flash memory - Code flash memory: 16 to 128 KB - Block size: 1 KB - Prohibition of block erase and rewriting (security function) - On-chip debug function - Self-programming (with boot swap function/flash shield window function) Data flash memory - Data flash memory: 4 KB - Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. - Number of rewrites: 1,000,000 times (TYP.) - Voltage of rewrites: VDD = 1.8 to 5.5 V High-speed on-chip oscillator - Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz - High accuracy: +/-1.0 % (VDD = 1.8 to 5.5 V, TA = -20 to +85°C) Operating ambient temperature - TA = -40 to +85°C (A: Consumer applications) - TA = -40 to +105°C (G: Industrial applications) Power management and reset function - On-chip power-on-reset (POR) circuit - On-chip voltage detector (LVD) (Select interrupt and reset from 14 levels) DMA (Direct Memory Access) controller - 4 channels - Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks Multiplier and divider/multiply-accumulator - 16 bits × 16 bits = 32 bits (Unsigned or signed) - 32 bits ÷ 32 bits = 32 bits...