R5F11EB8AFP Datasheet | Renesas

Features Ultra-low power consumption technology - VDD = single power supply voltage of 2.7 to 5.5 V - HALT mode - STOP mode - SNOOZE mode RL78 CPU core - CISC architecture with 3-stage pipeline - Minimum instruction execution time: Can be changed from high-speed (0.04167 μs: @ 24 MHz operation with high-speed on-chip oscillator) to low-speed (1.0 μs: @1 MHz operation with high-speed on-chip oscillator) - Multiply/divide/multiply & accumulate instructions are supported. - Address space: 1 MB - General-purpose registers: (8-bit register × 8) × 4 banks - On-chip RAM: 1.5 KB Code flash memory - Code flash memory: 8 to 16 KB - Block size: 1 KB - Prohibition of block erase and rewriting (security function) - On-chip debug function - Self-programming (flash shield window function) High-speed on-chip oscillator - Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 4 MHz, and 1 MHz - High accuracy: ±2.0% (VDD = 2.7 to 5.5 V, TA = -20 to +85°C) Operating ambient temperature - TA = -40 to +85°C Power management and reset function - On-chip power-on-reset (POR) circuit - On-chip voltage detector (LVD) (Select interrupt and reset from 6 levels) Event link controller (ELC) - Event signals of 18 to 19 types can be linked to the specified peripheral function. Serial interfaces - CSI: 1 channel - UART: 2 channels - Simplified I2C: 1 channel R01DS0241EJ0100 Rev. 1.00 Jul 31, 2014 Timer - 16-bit timer: 7 channels (Timer Array Unit (TAU): 4 channels, Timer RJ: 1 channel, Timer RD: 2...