R5F51104AGNE Datasheet PDF (32 MHz 32-bit RX MCUs)

R5F51104AGNE - 32 MHz 32-bit RX MCUs

This page provides the datasheet information for the R5F51104AGNE, a member of the R5F51105AGFM 32 MHz 32-bit RX MCUs family.

Description

CPU CPU Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per one clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-

Features

32-bit RX CPU core.
32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz.
Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations.
Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle).
Fast interrupt.
CISC Harvard architecture with five-stage pipeline.
Variable-length instruction format, ultra-compact code.
On-chip debuggi.

Datasheet Details

Part number	R5F51104AGNE
Manufacturer	Renesas
File Size	0.96 MB
Description	32 MHz 32-bit RX MCUs
Datasheet	R5F51104AGNE Datasheet
Additional preview pages of the R5F51104AGNE datasheet.

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Full PDF Text Transcription

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Datasheet RX110 Group Renesas MCUs R01DS0202EJ0110 Rev.1.10 Dec 10, 2014 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory, up to 5 comms channels, 12-bit A/D, RTC Features ■ 32-bit RX CPU core  32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz  Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations  Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with five-stage pipeline  Variable-length instruction format, ultra-compact code  On-chip debugging circuit ■ Low power consumption functions  Operation from a single 1.8 to 3.

Published: Jan 1, 2016 |