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Renesas Electronics Components Datasheet

R5F5110HADLM Datasheet

32 MHz 32-bit RX MCUs

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Datasheet
RX110 Group
Renesas MCUs
R01DS0202EJ0110
Rev.1.10
Dec 10, 2014
32 MHz 32-bit RX MCUs, 50 DMIPS,
up to 128 Kbytes of flash memory, up to 5 comms channels, 12-bit A/D, RTC
Features
32-bit RX CPU core
32 MHz maximum operating frequency
Capable of 50 DMIPS when operating at 32 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32-bit × 32-bit operations
Multiplication and division unit handles 32-bit × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with five-stage pipeline
Variable-length instruction format, ultra-compact code
On-chip debugging circuit
Low power consumption functions
Operation from a single 1.8 to 3.6 V supply
Three low power modes
Supply current
High-speed operating mode: 0.1 mA/MHz
Software standby mode: 0.35 μA
Recovery time from software standby mode: 4.8 μs
On-chip flash memory for code, no wait states
Operation at 32 MHz, read cycle of 31.25 ns
No wait states for reading at full CPU speed
8 to 128 Kbyte capacities
Programmable at 1.8 V
For instructions and operands
On-chip SRAM, no wait states
8 to 16 Kbyte capacities
Data transfer controller (DTC)
Four transfer modes
Transfer can be set for each interrupt source.
Reset and power supply voltage management
Six types including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External clock input frequency: Up to 20 MHz
Main clock oscillator frequency: 1 to 20 MHz
Sub-clock oscillator frequency: 32.768 kHz
Low-speed on-chip oscillator: 4 MHz
High-speed on-chip oscillator: 32 MHz±1% (20 to 85°C)
IWDT-dedicated on-chip oscillator: 15 kHz
Generate a dedicated 32.768-kHz clock for the RTC
On-chip clock frequency accuracy measurement circuit
(CAC)
Real-time clock (RTC)
30-second, leap year, and error adjustment functions
Calendar count mode or binary count mode selectable
Capable initiating exit from software standby mode
R01DS0202EJ0110 Rev.1.10
Dec 10, 2014
PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch
PLQP0064GA-A 14 × 14 mm, 0.8 mm pitch
PLQP0048KB-A 7 × 7 mm, 0.5 mm pitch
PWQN0048KB-A 7 × 7 mm, 0.5 mm pitch
PWQN0040KC-A 6 × 6 mm, 0.5 mm pitch
PWLG0064KA-A 5 × 5 mm, 0.5 mm pitch
PWLG0036KA-A 4 × 4 mm, 0.5 mm pitch
Independent watchdog timer (WDT)
15-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
On-chip functions for IEC 60730 compliance
Clock frequency accuracy measurement circuit, IWDT,
functions to assist in RAM testing, etc.
Up to five channels for communication
SCI: Asynchronous mode, clock synchronous mode,
smart card interface (up to seven channels)
I2C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (one channel)
RSPI: Up to 16 Mbps (one channel)
Up to 6 extended-function timers
16-bit MTU: Input capture/output compare,
phase counting mode (four channels)
16-bit CMT (two channels)
12-bit A/D converter
Up to 14 channels
1.0 μs minimum conversion speed
Double trigger (data duplication) function for motor
control
Temperature sensor
General I/O ports
5-V tolerant, open drain, input pull-up
Multi-function pin controller (MPC)
Multiple I/O pins can be selected for peripheral functions.
Unique ID
32-byte ID code for the MCU
Operating temperature range
 40 to 85C
 40 to 105°C
Page 1 of 103


Renesas Electronics Components Datasheet

R5F5110HADLM Datasheet

32 MHz 32-bit RX MCUs

No Preview Available !

RX110 Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1
Outline of Specifications (1/3)
Classification Module/Function
Description
CPU
CPU
Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per one clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit × 32-bit 64-bit
On-chip divider: 32-bit ÷ 32-bit 32 bits
Barrel shifter: 32 bits
Memory
ROM
Capacity: 8 K /16 K /32 K /64 K /96 K /128 Kbytes
32 MHz, no-wait memory access
Programming/erasing method:
Serial programming (asynchronous serial communication), self-programming
RAM
Capacity: 8 K /10 K /16 Kbytes
32 MHz, no-wait memory access
MCU operating mode
Single-chip mode
Clock
Clock generation circuit
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
and IWDT-dedicated on-chip oscillator
Oscillation stop detection: Available
Clock frequency accuracy measurement circuit (CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32,
64).
Resets
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
Voltage detection Voltage detection circuit
(LVDAa)
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Low power
consumption
Low power consumption
functions
Module stop function
Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Function for lower operating Operating power control modes
power consumption
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt
Interrupt controller (ICUb)
Interrupt vectors: 65
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt,
and IWDT interrupt)
16 levels specifiable for the order of priority
DMA
Data transfer controller
(DTCa)
Transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
R01DS0202EJ0110 Rev.1.10
Dec 10, 2014
Page 2 of 103


Part Number R5F5110HADLM
Description 32 MHz 32-bit RX MCUs
Maker Renesas
Total Page 30 Pages
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