R5F562T7AGFH Datasheet | Renesas

RX62T Group, RX62G Group Renesas MCUs R01DS0096EJ0200 100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC (3 S/H circuits, double data register, amplifier, parator): two units, 10-bit ADC one unit, the three ADC units are Rev.2.00 Jan 10, 2014 capable of simultaneous 7-ch. sampling, 100-MHz PWM (two three-phase plementary channels and four single-phase plementary channels or three three-phase plementary channels and one single-phase plementary channel) Features - 32-bit RX CPU core - Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz - Single precision 32-bit IEEE-754 floating point - Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations - Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle) - Fast interrupt - Divider (fastest instruction execution takes two CPU clock cycles) - Fast interrupt - CISC Harvard architecture with 5-stage pipeline - Variable-length instructions: Ultra-pact code - Supports the memory protection unit (MPU) - Background JTAG debugging plus high-speed tracing - Operating voltage - Single 3.3- or 5-V supply; 5-V analog supply is possible with 3.3-V products - Low-power design and architecture - Four low-power modes - On-chip main flash memory, no wait states - 100-MHz operation, 10-ns read cycle - No wait states for reading at full CPU speed - 64-Kbyte/128-Kbyte/256-Kbyte capacities - For instructions and operands - User code programmable via the SCI or JTAG - On-chip data flash memory - Max. 32 Kbytes, reprogrammable up to 30,000...