R5F562T7AGFK Renesas Datasheet

R5F562T7AGFK Key Features

• 32-bit RX CPU core
• Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz
• Single precision 32-bit IEEE-754 floating point
• Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations
• Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)
• Fast interrupt
• Divider (fastest instruction execution takes two CPU clock cycles)
• Fast interrupt
• CISC Harvard architecture with 5-stage pipeline
• Variable-length instructions: Ultra-pact code