R5F5630ADDFC
Features
RX630 Group
Renesas MCUs
R01DS0060EJ0160
Rev.1.60
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,
May 19, 2014 up to 2-MB flash memory, USB 2.0 full-speed function interface,
CAN, 10- & 12-bit A/D converter, RTC, up to 22 ms interfaces
Features
- 32-bit RX CPU core
- Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz
- Single precision 32-bit IEEE-754 floating point
- Two types of multiply-and-accumulation unit (between memories and between registers)
- 32-bit multiplier (fastest instruction execution takes one CPU clock cycle)
- Divider (fastest instruction execution takes two CPU clock cycles)
- Fast interrupt
- CISC Harvard architecture with 5-stage pipeline
- Variable-length instructions: Ultra-pact code
- Supports the memory protection unit (MPU)
- Two types of debugging interfaces: JTAG and FINE (two-line)
- Low-power design and architecture
- Operation from a single 2.7- to 3.6-V supply
- Low power consumption: A product...
