R5F5631YHDFB Datasheet | Renesas

Description

Maximum operating frequency: 100 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 Floating-point instructions: 8 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 x 32  64 bits On-chip divider: 32 / 32  32 bits Barrel shifter: 32 bits Memory protection unit (MPU) Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Capacity: ROMless, 256 Kbytes, 384 Kbytes, 512 Kbytes, 768 Kbytes, 1 Mbyte, 1.5 Mbytes, 2 Mbytes 100 MHz, no-wait access On-board programming: Four types Off-board programming (parallel programmer mode) (for products with 100 pins or more) Capacity: 64 Kbytes, 128 Kbytes, 192 Kbytes, 256 Kbytes 100 MHz, no-wait access E2 data flash MCU operating modes Clock Clock generation circuit Reset Capacity: 32 Kbytes Programming/erasing: 100,000 times Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode (software switching) Main clock oscillator, subclock oscillator, low-speed/high-speed on-chip oscillator, PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator Main-clock oscillation stoppage detection Separate frequency-division and multiplication settings for the system clock (ICLK), peripheral module clock (PCLK), FlashIF clock (FCLK) and external bus clock (BCLK) The CPU and other bus masters run in synchronization with the system clock (ICLK): Up to 100 MHz Peripheral modules run in synchronization with the peripheral module clock (PCLK): Up to 50 MHz Flash IF run in synchronization with the flashIF clock (FCLK): Up to 50 MHz Devices connected to the external bus run in synchronization with the external bus clock (BCLK): Up to 50 MHz RES# pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer reset, watchdog timer reset, deep software standby reset, and software reset Voltage detection circuit When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or internal interrupt is generated. R01DS0098EJ0180 Rev.1.80 May 13, 2014 Page 2 of 208 RX63N Group, RX631 Group 1.