R5F5651CHDLJ Overview
120 MHz Capable of 240 DMIPS in operation at 120 MHz Single precision 32-bit IEEE-754 floating point Two types of multiply-and-accumulation unit (between memories and between registers) 32-bit multiplier (fastest instruction execution takes one CPU clock cycle) Divider (fastest instruction execution takes two CPU clock cycles) Fast interrupt CISC Harvard architecture with 5-stage pipeline ...
R5F5651CHDLJ Key Features
- 32-bit RXv2 CPU core
- Max. operating frequency: 120 MHz Capable of 240 DMIPS in operation at 120 MHz
- Single precision 32-bit IEEE-754 floating point
- Two types of multiply-and-accumulation unit (between memories and between registers)
- 32-bit multiplier (fastest instruction execution takes one CPU clock cycle)
- Divider (fastest instruction execution takes two CPU clock cycles)
- Fast interrupt
- CISC Harvard architecture with 5-stage pipeline
- Variable-length instructions: Ultra-pact code
- Supports the memory protection unit (MPU)