RC19020A072 Datasheet | Renesas

features , easing system design. They can drive both source-terminated and doubleterminated loads, operating up to 400MHz. The family offers 2, 4, 8, 13, 16, 20, and 24 Low Power (LP) HCSL output pairs in 3 × 3 mm to 10 × 10 mm packages. The RC190xx devices offer higher output counts in smaller packages pared to earlier buffer families. The buffers support both mon Clock (CC) and Independent Reference (IR) PCIe clock architectures. Applications - Cloud/High-performance puting - n VME storage - Networking - Accelerators Features - PCIe Gen5 additive phase jitter: 6fs RMS - PCIe Gen6 additive phase jitter: 4fs RMS - DB2000Q additive phase jitter: 10fs RMS - 12k Hz to 20MHz additive phase jitter: 30fs RMS at 156.25MHz - Power Down Tolerant (PDT) inputs - Flexible Startup Sequencing (FSS) - Automatic Clock Parking (ACP) upon loss of CLKIN - Spread-spectrum tolerant - CLKIN accepts HCSL or LVDS signal levels - -40 to +105°C, 3.3V ±10% operation - All devices except RC19002: - Selectable output slew rate via pin/SMBus - 4-wire Side-Band Interface supports high-speed serial output enable and device daisy-chaining - 9 SMBus addresses plus write protection - 85Ω or 100Ω (A100 suffix) output impedance - Pin-selectable slew rate - RC19002: Pin-selectable output impedance C LKI Nb CLKIN Note 3 SADR_tri[1 :0] SC LK SDATA PWR GD _PW R DN b Note 1, 3 SLE WRATE_ SEL Note 2, 3 Note 3 OEb [m:n] SBI _I N SBI_CLK SHFT_ LDb SBI_ENQ Clock Dete ct Control Logic SM Bus Inte rface Output Co ntro...