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Renesas Electronics Components Datasheet

HD74LV2GT126A Datasheet

Dual Bus Buffer

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HD74LV2GT126A
Dual Bus Buffer with 3–state Output /
CMOS Logic Level Shifter
REJ03D0149–0200Z
(Previous ADE-205-677A (Z))
Rev.2.00
Oct.23.2003
Description
The HD74LV2GT126A has dual bus buffer with 3–state output in a 8 pin package. Output is disabled
when the associated output enable (OE) input is low. To ensure the high impedance state during power up
or power down, OE should be connected to GND through a pull-down resistor; the minimum value of the
resistor is determined by the current souring capability of the driver. The input protection circuitry on this
device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator
from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while
operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for the
battery powered products (e.g., notebook computers), and the low power consumption extends the battery
life.
Features
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
Logic-level translate function
3.0 V CMOS logic 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic 3.3 V CMOS logic (@VCC = 3.3 V)
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
HD74LV2GT126AUSE SSOP-8 pin
Package Code
TTP-8DBV
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Rev.2.00, Oct.23.2003, page 1 of 1


Renesas Electronics Components Datasheet

HD74LV2GT126A Datasheet

Dual Bus Buffer

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HD74LV2GT126A pdf
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HD74LV2GT126A
Outline and Article Indication
• HD74LV2GT126A
Index band
Lot No.
SSOP-8
Function Table
Inputs
OE
H
H
L
H : High level
L : Low level
X : Immaterial
Z : High impedance
A
H
L
X
YMW
T26
Y : Year code
(the last digit of year)
M : Month code
W : Week code
Marking
Output Y
H
L
Z
Rev.2.00, Oct.23.2003, page 2 of 8


Part Number HD74LV2GT126A
Description Dual Bus Buffer
Maker Renesas Technology
Total Page 9 Pages
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HD74LV2GT126A Datasheet PDF
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