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Renesas Electronics Components Datasheet

M5M5V416CWG-55HI Datasheet

CMOS STATIC RAM

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2003.08.21 Ver. 7.0
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RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5V416CWG is a f amily of low v oltage 4-Mbit static RAMs - Single 2.7~3.6V power supply
organized as 262144-words by 16-bit, f abricated by Renesas's - Small stand-by current: 0.2µA (3.00V, ty p.)
high-perf ormance 0.18µm CMOS technology .
- No clocks, No ref resh
The M5M5V416C is suitable f or memory applications where a
- Data retention supply v oltage =2.0V
simple interf acing , battery operating and battery backup are the - All inputs and outputs are TTL compatible.
important design objectiv es.
- Easy memory expansion by S1#, S2, BC1# and BC2#
M5M5V416CWG is packaged in a CSP (chip scale package),
- Common Data I/O
with the outline of 7.0mm x 8.5mm, ball matrix of 6 x 8 (48ball) - Three-state outputs: OR-tie capability
and ball pitch of 0.75mm. It giv es the best solution f or
- OE# prev ents data contention in the I/O bus
a compaction of m ounting area as well as f lexibility of wiring
- Process technology : 0.18µm CMOS
pattern of printed circuit boards.
- Package: 48ball 7.0mm x 8.5mm CSP
Version,
Operating
temperature
Part name
I-version
-40 ~ +85°C
M5M5V416CWG -55HI
M5M5V416CWG -70HI
Power
Supply
Access time
max.
Stand-by c urrent (µA)
* Typical(3.0V)
Ratings (max. @3.6V)
25°C 40°C Voltage 25°C 40°C 70°C 85°C
Activ e
current
Icc1
(3.0V, ty p.)
2.7 ~ 3.6V
55ns
70ns
3.0V 1.0 2.0 10 20
30mA
0.2 0.4 3.3V 1.5 2.5 10
20
(10MHz)
5mA
3.6V 2.5 4.0 10 20 (1MHz)
PIN CONFIGURATION
* Typical parameter indicates the value for the center
of distribution, and not 100% tested.
(TOP VIEW)
1 23 456
A BC1# OE#
A0
A1
A2 S2
B DQ16 BC2#
A3
A4 S1# DQ1
C DQ14 DQ15
A5
A6 DQ2 DQ3
D GND DQ13
A17
A7 DQ4 VCC
E VCC
DQ12
NC or
GND
A16
DQ5 GND
F DQ11 DQ10 A14 A15 DQ7 DQ6
G DQ9
N.C. A12
A13 W#
DQ8
H N C A8 A9 A10 A11 N.C.
Outline: 48FJA
NC: No Connection
*Don't connect E3 ball to voltage level more than 0V.
Pin Function
A0 ~ A17 Address input
DQ1 ~ DQ16 Data input / output
S1# Chip select input 1
S2 Chip select input 2
W# Write control input
OE#
BC1#
Output enable input
Lower By te (DQ1 ~ 8)
BC2# Upper By te (DQ9 ~ 16)
Vcc Power supply
GND
Ground supply
1


Renesas Electronics Components Datasheet

M5M5V416CWG-55HI Datasheet

CMOS STATIC RAM

No Preview Available !

2003.08.21 Ver. 7.0
RENESAS LSIs
M5M5V416CWG -55HI, -70HI
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V416CWG is organized as 262144-words by
16-bit. These dev ices operate on a single +2.7~3.6V power
supply , and are directly TTL compatible to both input and
output. Its f ully static circuit needs no clocks and no
ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S1#, S2 , W# and
OE#. Each mode is summarized in the f unction table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S1# and the high lev el S2. The address(A0~A17)
must be set up bef ore the write cy c le and must be stable
during the entire cy c le.
A read operation is executed by s etting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2# and
S1# and S2 are in an activ e state(S1#=L,S2=H).
When setting BC1# at the high lev el and other pins are
in an activ e stage , upper-by t e are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2# at a
high lev el and other pins are in an activ e stage, lower-
by t e are in a selectable mode and upper-by te are in a
non-selectable mode.
BLOCK DIAGRAM
When setting BC1# and BC2# at a high lev el or S1# at a
high lev el or S2 at a low lev el, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by BC1#, BC2# and S1#, S2.
The power supply c urrent is reduced as low as 0.2µA(25°C,
ty pical), and the memory data can be held at +2V power
supply , enabling battery back-up operation during power
f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1# S2 BC1# BC2# W# OE# Mode DQ1~8 DQ9~16 Icc
X L X X X X Non selection High-Z High-Z Standby
H H X X X X Non selection High-Z High-Z Standby
X X H H X X Non selection High-Z High-Z Standby
L H L H L X Write Din High-Z Activ e
L H L H H L Read Dout High-Z Activ e
LH L HH H
High-Z High-Z Activ e
L H H L L X Write High-Z Din Activ e
L H H L H L Read High-Z Dout Activ e
LH H L HH
High-Z High-Z Activ e
L H L L L X Write Din Din Activ e
L H L L H L Read Dout Dout Activ e
LH L L HH
High-Z High-Z Activ e
(note) "H" and "L" in this table mean VIH and VIL, respectiv ely .
"X" in this table should be "H" or "L".
A0
A1
MEMORY ARRAY
262144 WORDS
x 16 BITS
A16 -
A17
DQ
1
DQ
8
DQ
9
S1#
S2
CLOCK
GENERATOR
DQ
16
BC1#
BC2#
Vcc
W#
OE#
GND
2


Part Number M5M5V416CWG-55HI
Description CMOS STATIC RAM
Maker Renesas Technology
Total Page 9 Pages
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