HXB15H1G160CF
Key Features
- 1.5 V ±0.075 V Power Supply
- Off-Chip-Driver impedance adjustment (OCD) and
- 5 V ±0.075 V (SSTL_15) compatible I/O
- DRAM organizations with 8/16 data in/outputs
- Double Data Rate architecture: - two data transfers per clock cycle - eight internal banks for concurrent operation
- Programmable CAS Latency: 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported
- Programmable Burst Length: 4/8 with both nibble sequential and interleave mode.
- Differential clock inputs (CK and CK)
- Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read On-Die-Termination (ODT) for better signal quality
- Auto-Precharge operation for read and write bursts
