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74AC373 Datasheet

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

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74AC373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s 50TRANSMISSION LINE DRIVING
BM
CAPABILITY
(Plastic Package)
(Micro Package)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
ORDER CODES :
74AC373B
74AC373M
tPLH tPHL
(OE).
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
s IMPROVED LATCH-UP IMMUNITY
While the LE inputs is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q
outputs will be latched precisely or inversely at
the logic level of D input data. While the (OE)
input is low, the 8 outputs will be in a normal logic
DESCRIPTION
state (high or low logic level) and while high level
TONsihOlCiceTNoAnALCIgNa3DVt7-eET3aYRniPsTdEINadnLGoAuabTdflCaevb-Halranicwycaeeittrhdemd3heiSgtwahTilt-AwhsTpireEisneugOdbCU-Cm2TMMiPcwOOrUwowSSTn.DataSheet4tTScUho.hpceomimesoepuddotenpveuCicntMsetsOwi.sSilldbesesyiisngtneaemhdsigtohwiiinmthtepreTfadTcaLencdaeinrsedtcattlNye.MHOigSh
technology. It is ideal for low power applications
mantaining high speed operation similar to All inputs and outputs are equipped with
equivalent Bipolar Schottky TTL.
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
These 8 bit D-Type latch are controlled by a latch voltage.
enable input (LE) and an output enable input
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1997
1/10


STMicroelectronics Electronic Components Datasheet

74AC373 Datasheet

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

No Preview Available !

74AC373
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2, 5, 6,
9, 12, 15,
16, 19
3, 4, 7,
8, 13, 14,
17, 18
11
10
20
SYMBOL
OE
Q0 to Q7
NAME AND FUNCTION
3 State Output Enable
Input (Active LOW)
Data Inputs
D0 to D7 3 State Outputs
LE
GND
VCC
Latch Enable
Input
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
IN PUT S
OE LE
D
HXX
LLX
LHL
LHH
X: DON’T CARE
Z: HIGH IMPEDANCE
*: Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE INPUT IS TAKEN LOW LOGIC LEVEL.
OUTPUTS
Q
Z
NO CHANGE
L
H
LOGIC DIAGRAMS
2/10


Part Number 74AC373
Description OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
Maker STMicroelectronics
Total Page 10 Pages
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