STMicroelectronics Electronic Components Datasheet

9202 Datasheet

Flash Programmable System Devices with 8032 Microcontroller Core

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UPSD3254A, UPSD3254BV

UPSD3253B, UPSD3253BV

Flash Programmable System Devices

with 8032 Microcontroller Core

FEATURES SUMMARY

s The uPSD325X devices combine a Flash PSD

architecture with an 8032 microcontroller core.

The uPSD325X devices of Flash PSDs feature

dual banks of Flash memory, SRAM, general

purpose I/O and programmable logic, supervi-

sory functions and access via USB, I2C, ADC,

DDC and PWM channels, and an on-board

8032 microcontroller core, with two UARTs,

three 16-bit Timer/Counters and two External

Interrupts. As with other Flash PSD families, the

uPSD325X devices are also in-system pro-

grammable (ISP) via a JTAG ISP interface.

s Large 32KByte SRAM with battery back-up

option

Figure 1. 52-lead, Thin, Quad, Flat Package

TQFP52 (T)

s Dual bank Flash memories

– 128KByte or 256KByte main Flash memory

– 32KByte secondary Flash memory

s Content Security

– Block access to Flash memory

www.DataSheet4U.com

Figure 2. 80-lead, Thin, Quad, Flat Package

s Programmable Decode PLD for flexible address

mapping of all memories within 8032 space.

s High-speed clock standard 8032 core (12-cycle)

s USB Interface (some devices only)

s I2C interface for peripheral connections

s 5 Pulse Width Modulator (PWM) channels

s Analog-to-Digital Converter (ADC)

s Standalone Display Data Channel (DDC)

s Six I/O ports with up to 46 I/O pins

s 3000 gate PLD with 16 macrocells

TQFP80 (U)

s Supervisor functions with Watchdog Timer

s In-System Programming (ISP) via JTAG

s Zero-Power Technology

s Single Supply Voltage

– 4.5 to 5.5V

– 3.0 to 3.6V

September 2003

Rev. 1.2

1/175

STMicroelectronics Electronic Components Datasheet

9202 Datasheet

Flash Programmable System Devices with 8032 Microcontroller Core

No Preview Available !

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

TABLE OF CONTENTS

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

uPSD325X Devices Product Matrix (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

TQFP52 Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

TQFP80 Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

80-Pin Package Pin Description (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

52 PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Memory Map and Address Space (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8032 MCU Registers (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Configuration of BA 16-bit Registers (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Stack Pointer (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PSW (Program Status Word) Register (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Interrupt Location of Program Memory (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

XRAM-DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

RAM Address (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Direct Addressing (Figure 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Indirect Addressing (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Indexed Addressing (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Arithmetic Instructions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Logical Instructions (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Transfer Instructions that Access Internal Data Memory Space (Table 6.) . . . . . . . . . . . . . . 25

Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes) (Table 7.) . . . . . . . 26

Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes) (Table 8.) . . . . . . . . 26

Shifting a BCD Number One Digit to the Right (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Data Transfer Instruction that Access External Data Memory Space (Table 10.) . . . . . . . . . . . . . . 27

Lookup Table READ Instruction (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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9202 Datasheet

Flash Programmable System Devices with 8032 Microcontroller Core

9202 Datasheet

Flash Programmable System Devices with 8032 Microcontroller Core

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