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CB45000 Datasheet

HCMOS6 STANDARD CELLS

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® CB45000 SERIES
HCMOS6 STANDARD CELLS
FEATURES
s 0.35 micron 5 layer metal HCMOS6 process,
retrograde well technology, low resistance
salicided active areas and polysilicide gates.
s 3.3 V optimized transistor with 5 V I/O inter-
face capability
s 2 - input NAND delay of 160 ps (typ) with
fanout = 2.
s Broad I/O functionality including Low Voltage
CMOS, Low Voltage TTL and LVDS. Driving
capability to ISA, EISA, PCI, MCA, and SCSI
interface levels
s High drive I/O; capability of sinking up to 24
mA with slew rate control, current spike sup-
pression and impedance matching.
s Generators to support Single Port RAM,
Dual Port RAM, and ROM with BIST options.
s DRAM integration in ASIC methodology
s Extensive embedded function library includ-
ing ST DSP and micro cores, third party
micros and Synopsys synthetic libraries.
s Fully independent power and ground config-
urations for inputs, core and outputs.
s I/O ring capability up to 1000 pads.
s Latchup trigger current > +/- 500 mA.
ESD protection > +/- 4000 volts typical value
s Oscillators for wide frequency spectrum.
s Broad range of 500+ SSI cells
s Design For Test features including IEEE
1149.1 JTAG Boundary Scan architecture.
s Cadence, Mentor and Synopsys based
design systems with interfaces from multiple
workstations.
s Broad ceramic and plastic package range.
ROM
DSP
DPRAM
ST20
CB45000 Super-Integration
Cost Effective Product
s Architecture Partitioning
s Trouble free integration
s Application Specific
Your Product is Unique
s User specified cell integration
s Design Confidentiality
s IP fully re-usable
March 1998
1/16


STMicroelectronics Electronic Components Datasheet

CB45000 Datasheet

HCMOS6 STANDARD CELLS

No Preview Available !

CB45000 SERIES
GENERAL DESCRIPTION
The CB45000 standard cell series uses a high
performance, low voltage, 5 level metal,
HCMOS6 0.35 micron process to achieve sub-
nanosecond internal speeds while offering very
low power dissipation and high noise immunity.
With an average routed logic density of 14000
gates/mm2, the CB45000 family allows the
design of highly complex devices. The potential
available gate count ranges above 3 Million
equivalent gates. Devices can operate over a Vdd
voltage range of 2.7 to 3.6 volts.
The I/O count for this array family ranges to over
750 signals and 1000 pins based upon the
package technology utilized. A flexible I/O
approach has been developed to provide an
optimum solution for today’s complex system
problems of drive levels and specialized interface
standards.
The product offers a variable bonding approach
supporting pad spacings from 80µ upwards and
supports staggered pad rows to address today’s
bonding technologies. Additional flexibility to
support 65µ and 50µ pad spacing will be
available in the near future.
The I/O can be configured for circuits ranging
from low voltage CMOS and TTL to low swing
differential circuits (LVDS) and the 1Gigabit per
second high speed link. Standards like SCSI, 3.3
and 5 Volt PCI and other 5.0 Volt interfaces are
currently being addressed.
Figure 1
Process Overview
Metal 5 : Al-Cu
Metal 4 : Al-Cu
Metal 3 : Al-Cu
Metal 2 : Al-Cu
Metal 1 : W
2/16
®


Part Number CB45000
Description HCMOS6 STANDARD CELLS
Maker STMicroelectronics
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CB45000 Datasheet PDF






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