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STMicroelectronics Electronic Components Datasheet

FC106 Datasheet

Fibre Channel Transceiver 1.0625 GBaud

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® FC106
Fibre Channel Transceiver 1.0625 GBaud
FEATURES
s Serial Link Transceiver
q serializer and deserializer
q implementing the Fibre Channel FC0
and FC1 layers
s Direct support for 1.0625 GBaud Fibre
Channel (ANSI X3.230-1994) rates
s Fibre Channel 10-bit Interface (ANSI
TR/X3.18-199X)
s Direct interfaces to optical tranceivers
s Plesiochronous mode operation
q transmitter and receiver clock
frequencies may differ by up to 100 ppm
s Integrated Fibre Channel 8b/10b
encode/decode (optional use through
JTAG)
s Byte and word synchronization of
incoming serial stream
s Supports any DC-balanced encoding
scheme
s Internal Loop-Back for Self-Test
s Random Pattern Auto-Test
s Optional integrated impedance
adaptation to transmission line
characteristics (50 or 75 ohms)
s TTL compatible parallel I/O’s
s JTAG Test Access Port
s 0.35µ CMOS Technology for low cost
and low power
s PQFP package available in two sizes:
14x14 mm (FC106/14) or 10x10 mm
(FC106/10)
PRELIMINARY DATA
Receive
Byte
Clock
Parallel Interface
REFCLK
10 bits
8 bit / 10 bit
DECODER
(optional)
8 bit / 10 bit
ENCODER
(optional)
DESER IALIZER
CLOCK RECOVERY
BYTE AND WORD
ALIGNEMENT
SERIALI ZER
AND CLOCK
FREQ UENCY
MULTIPLIC ATION
FC 106
1.0625 Gbaud
Serial data over copper
or optical cables
APPLICATIONS
s Fibre Channel Arbitrated Loop
s Fibre Channel fabric
s Transmission schemes encoding
bytes as 10-bit characters to form a
DC-balanced stream
s High performance backplane
interconnect
1/32
September 98
Revision 1.2


STMicroelectronics Electronic Components Datasheet

FC106 Datasheet

Fibre Channel Transceiver 1.0625 GBaud

No Preview Available !

FC106
Table of Contents
1 General Description - - - - - - - - - - - - - - - - - - - - - - 4
2 Interface Diagram - - - - - - - - - - - - - - - - - - - - - - - 6
3 Functional Description - - - - - - - - - - - - - - - - - - - - 7
3.1 Block diagram - - - - - - - - - - - - - - - - - - - - - - - 8
3.2 Input latches - - - - - - - - - - - - - - - - - - - - - - - - 8
3.3 8bit/10bit Encoder/Decoder - - - - - - - - - - - - - - - - - 9
3.4 DLL clock generator - - - - - - - - - - - - - - - - - - - - 9
3.5 Serializer functional description and reference clock - - - - - 9
3.6 Serializer latches and XOR-tree - - - - - - - - - - - - - - 10
3.7 Serial input multiplexer - - - - - - - - - - - - - - - - - - 10
3.8 Deserializer functional description - - - - - - - - - - - - - 10
3.9 Bit alignment - - - - - - - - - - - - - - - - - - - - - - - 11
3.10 Byte and word alignment - - - - - - - - - - - - - - - - 12
3.11 Clock recovery - - - - - - - - - - - - - - - - - - - - - 12
3.12 Serial input-output buffer - - - - - - - - - - - - - - - - 13
3.13 I/O impedance control - - - - - - - - - - - - - - - - - - 14
3.14 Self-test - - - - - - - - - - - - - - - - - - - - - - - - - 15
4 Serial I/O Electrical Model - - - - - - - - - - - - - - - - - 16
5 Electrical Specifications - - - - - - - - - - - - - - - - - - 17
5.1 Absolute maximum ratings - - - - - - - - - - - - - - - - 17
5.2 Operating conditions - - - - - - - - - - - - - - - - - - - 17
5.3 DC characteristics - - - - - - - - - - - - - - - - - - - - 18
2/32
September 98
Revision 1.2


Part Number FC106
Description Fibre Channel Transceiver 1.0625 GBaud
Maker STMicroelectronics
Total Page 30 Pages
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