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STMicroelectronics Electronic Components Datasheet

M24M01-V Datasheet

1 Mbit Serial IC Bus EEPROM

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M24M01
1 Mbit Serial I²C Bus EEPROM
FEATURES SUMMARY
s 400 kHz High Speed Two Wire I2C Serial
Interface
s Single Supply Voltage:
– 2.7V to 3.6V for M24M01-V
– 1.8V to 3.6V for M24M01-S
s Write Control Input
s BYTE and PAGE WRITE (up to 128 Bytes)
s RANDOM and SEQUENTIAL READ Modes
s Self-Timed Programming Cycle
s Automatic Address Incrementing
s Enhanced ESD/Latch-Up Behavior
s More than 100000 Erase/Write Cycles
s More than 40 Year Data Retention
Figure 1. Packages
LGA
LGA8 (LA)
January 2003
1/19


STMicroelectronics Electronic Components Datasheet

M24M01-V Datasheet

1 Mbit Serial IC Bus EEPROM

No Preview Available !

M24M01
SUMMARY DESCRIPTION
The M24M01 is a 1 Mbit (131,072 x 8) electrically
erasable programmable memory (EEPROM) ac-
cessed by an I2C-compatible bus.
Figure 2. Logic Diagram
VCC
2
E1-E2
SCL
WC
M24M01
SDA
VSS
AI04048B
When writing data to the memory, the device in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Figure 3. LGA Connections
DU
E1
E2
VSS
M24M01
18
27
36
45
VCC
WC
SCL
SDA
AI04051C
Table 1. Signal Names
E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC Write Control
VCC
VSS
Supply Voltage
Ground
These devices are compatible with the I2C memo-
ry protocol. This is a two wire serial interface that
uses a bi-directional data bus and serial clock. The
devices carry a built-in 4-bit Device Type Identifier
code (1010) in accordance with the I2C bus defini-
tion.
The device behaves as a slave in the I2C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 2),
terminated by an acknowledge bit.
Note: 1. DU = Don’t Use (should be left unconnected, or tied to
VSS)
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until VCC has reached the POR
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when VCC drops from the operating
voltage, below the POR threshold value, all oper-
ations are disabled and the device will not respond
to any command. A stable and valid VCC must be
applied before applying any logic signal.
When the power supply is turned on, VCC rises
from VSS to VCC(min), passing through a value Vth
in between. The device ignores all instructions un-
til a time delay of tPU has elapsed after the mo-
ment that VCC rises above the Vth threshold.
However, the correct operation of the device is not
guaranteed if, by this time, VCC is still below
VCC(min).No instructions should be sent until the
later of:
– tPU after VCC passed the Vth threshold
– VCC passed the VCC(min) level
These values are specified in Table 9.
2/19


Part Number M24M01-V
Description 1 Mbit Serial IC Bus EEPROM
Maker STMicroelectronics
Total Page 19 Pages
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