M54HC77
M54HC77 is 4-BIT D-TYPE LATCH manufactured by STMicroelectronics.
M54HC77 M74HC77
4-BIT D-TYPE LATCH
- . . .
HIGH SPEED t PD = 10 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 m A (MIN.) BALANCED PROPAGATION DELAYS t PLH = t PHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION PATIBLE WITH 54/74LS77
B1R (Plastic Package)
F1R (Ceramic Package)
M1R (Micro Package)
C1R (Chip Carrier)
ORDER CODES : M54HC77F1R M74HC77M1R M74HC77B1R M74HC77C1R
DESCRIPTION The M54/74HC77 is a high speed CMOS 4-BIT DTYPE LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL bined with true CMOS low power consumption. It contains two groups of 2-bit latches controlled by an enable input (G1
- 2 or G3
- 4). These two latch groups can be used in different circuits. The data applied to the data inputs (1D, 2D, or 3D, 4D) are transfered to the Q outputs (1Q, 2Q, or 3Q, 4Q) respectively when the enable input (G1
- 2 or G3
- 4) is taken high. The Q outputs will follow the data inputs as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data inputs is retained at the Q outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS (top view)
NC = No Internal Connection
October 1992
1/10
M54/M74HC77
TRUTH TABLE
INPUTS D L H X
X: Don’t Care
IEC LOGIC SYMBOL
OUTPUTS FUNCTION
Q L H Qn LATCH
PIN DESCRIPTION
PIN No 1, 2, 5, 6 3 7, 10 8, 9, 13, 14 12 11 4 SYMBOL 1D to 4D G3
- 4 NC 1Q to 4Q G1
- 2 GND V CC NAME AND FUNCTION Data Inputs Latch Enable Input, Latches 3 and 4 No Internal Connection Latch Outputs Latch Enable Input, Latches 1 and 2 Ground (0V) Positive Supply Voltage
LOGIC...
