M74HC73 Datasheet | STMicroelectronics

DESCRIPTION The M54/74HC73 is a high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL bined with true CMOS low power consumption. Depending on the logic level applied to J and K inputs, this device changes state on the negative going transition of clock input pulse (CK). The clear function is acplished independently of the clock condition when the clear input (CLR) is taken low. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection October 1992 1/11 M54/M74HC73 TRUTH TABLE INPUTS CLR L H H H H H X: Don’t Care OUTPUTS K X L H L H X CK X Q L Qn L H Qn Qn Q H Qn H L Qn Qn J X L L H H X FUNCTION CLEAR NO CHANGE --TOGGLE NO CHANGE PIN DESCRIPTION PIN No 1, 5 2, 6 12, 9 13, 8 14, 7, 3, 10 11 4 SYMBOL 1CK, 2CK 1CLR, 2CLR 1Q, 2Q 1Q, 2Q 1J, 2J, 1K, 2K GND V CC NAME AND FUNCTION Clock Input Asyncronous Reset Inputs True Flip-Flop Outputs plement Flip-Flop Outputs Synchronous Inputs; Flip-Flop 1 And 2 Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOL LOGIC DIAGRAM 2/11 M54/M74HC73 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500 (- ) -65 to +150 300 Unit V V V m A m A m A m A m W o o Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (- ) 500 m W: ≅ 65 o C derate to 300 m W by 10m W/o C: 65 o C to 85 o C REMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Parameter Supply Voltage Input Voltage Output Voltage...