M74HCT164 Datasheet | STMicroelectronics

DESCRIPTION The M54/74HCT164 is a high speed CMOS 8 BIT SIPO SHIFT REGISTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL bined with true CMOS low power consumption. The HCT164 is an 8 bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B), either of these inputs can be used as an active high enable for data entry through the other input. An unused input must be high, or both inputs connected together. Each low-to-high transition on the clock input shifts data one place to the right and enters into QA, the logic NAND of the two data inputs (A - B), the data that existed before the rising clock edge. A low level on the clear input overrides all other inputs and clears the register asynchronously, forcing all Q outputs low. All inputs are equipped with protection circuits against static discharge and transient excess voltage. This integrated circuit has input and output characteristics that are fully patible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS ponents. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. February 1993 PIN CONNECTIONS (top view) NC = No Internal Connection 1/12 M54/M74HCT164 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS CLEAR L H H H H CLOCK X SERIAL IN A X X L X H B X X X L H L L H QA L QB L QAn QAn QAn OUTPUS QH L QGn QGn QGn NO CHANGE X: Don’t Care QAn - QGn : The level of QA -QG, respectively. before the most-recent transition of th clock. LOGIC DIAGRAM 2/12 M54/M74HCT164 PIN DESCRIPTION PIN No 1, 2 3, 4, 5, 6, 10, 11, 12, 13 8 9 7 14 SYMBOL A, B QA to QH NAME AND FUNCTION Data Inputs Outputs IEC LOGIC SYMBOL CLOCK CLEAR GND V CC Clock Input (LOW to HIGH, Edge-triggered) Master Reset Input Ground (0V)...