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STMicroelectronics Electronic Components Datasheet

PSD854F2 Datasheet

Flash in-system programmable (ISP) peripherals for 8-bit MCUs

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PSD8XXFX
Flash in-system programmable (ISP)
peripherals for 8-bit MCUs, 5 V
Features
Flash in-system programmable (ISP)
peripheral for 8-bit MCUs
Dual bank Flash memories
)– Up to 2 Mbit of primary Flash memory (8
t(suniform sectors, 32K x8)
c– Up to 256 Kbit secondary Flash memory (4
uuniform sectors)
rod– Concurrent operation: read from one
memory while erasing and writing the other
PUp to 256 Kbit SRAM
te27 reconfigurable I/Oports
oleEnhanced JTAG serial port
sPLD with macrocells
Ob– Over 3000 gates of PLD: CPLD and DPLD
-– CPLD with 16 output macrocells (OMCs)
)and 24 input macrocells (IMCs)
t(s– DPLD - user defined internal chip select
cdecoding
du27 individually configurable I/O port pins
roThey can be used for the following functions:
– MCU I/Os
P– PLD I/Os
te– Latched MCU address output
le– Special function I/Os.
so– 16 of the I/O ports may be configured as
Ob open-drain outputs.
PQFP52 (M)
PLCC52 (J)
TQFP64 (U)
Programmable power management
Packages are ECOPACK®
Table 1. Device summary
Reference
Part number
PSD813F2
PSD813F4
In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows
PSD813F5
full-chip in-system programmability
PSD8XXFX
PSD833F2
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK cable with PC
Page register
PSD834F2
PSD853F2
PSD854F2
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
May 2009
Doc ID 7833 Rev 7
1/128
www.st.com
1


STMicroelectronics Electronic Components Datasheet

PSD854F2 Datasheet

Flash in-system programmable (ISP) peripherals for 8-bit MCUs

No Preview Available !

Contents
Contents
PSD8XXFX
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
t(s)3.3 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
c3.4 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
du3.5 MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ro3.6 JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
P3.7 In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
lete3.8 Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
bso4 Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
- O5 PSD register description and address offset . . . . . . . . . . . . . . . . . . . . 24
ct(s)6 Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
du6.1 Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ro6.2 Description of primary Flash memory and secondary Flash memory . . . 27
te P6.3 Memory block select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
le 6.3.1 Ready/Busy (PC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
o 6.3.2 Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Obs7 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3 Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.4 Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.5 Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.6 Reading the Erase/Program Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.7 Data Polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/128
Doc ID 7833 Rev 7


Part Number PSD854F2
Description Flash in-system programmable (ISP) peripherals for 8-bit MCUs
Maker STMicroelectronics
Total Page 30 Pages
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