SPC584C70E3
Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.
Key Features
- AEC-Q100 qualified
- High performance e200z420n3 dual core - 32-bit Power Architecture technology CPU - Core frequency as high as 180 MHz - Variable Length Encoding (VLE)
- 4224 KB (4096 KB code flash + 128 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
- 176 KB HSM dedicated flash memory (144 KB code + 32 KB data)
- 384 KB on-chip general-purpose SRAM (in addition to 128 KB core local data RAM: 64 KB included in each CPU)
- Multi-channel direct memory access controller (eDMA) with 64 channels
- 1 interrupt controller (INTC)
- Comprehensive new generation ASIL-B safety concept - ASIL-B of ISO 26262 - FCCU for collection and reaction to failure notifications - Memory Error Management Unit (MEMU) for collection and reporting of error events in memories - Cyclic redundancy check (CRC) unit
- Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC
- Body cross triggering unit (BCTU) - Triggers ADC conversions from any eMIOS channel - Triggers ADC conversions from up to 2 dedicated PIT_RTIs
