32-BIT RISC CPU WITH 24-BIT LINEAR MEMORY ADDRESSING I 368 KBYTES USER ROM I 16 KBYTES USER RAM I 256K KBYTES USER EEPROM 32-BIT RISC CPU I DUAL INSTRUCTION SET, JAVACARD.

Figure 2. SmartJ™ Platform EEPROM Architecture SECURITY Memories are accessed via two different buses, allowing simult.

The ST22N256 is a member of the SmartJ™ platform using a 32-bit Reduced Instruction Set Computer (RISC) core to execute both Native RISC instructions and JavaCard™ 2.x Technology instruction (byte codes) directly. Direct JavaCard™ byte code execution.

ST22N144

ST220-100T4MI

ST220-50T2MI

ST2202

ST2221A

ST2221C

ST2225A

ST2226A

ST2226B

ST223C

ST223S

ST2244

ST2245