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STA120 Datasheet

DIGITAL AUDIO INTERFACE RECEIVER

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STA120
DIGITAL AUDIO INTERFACE RECEIVER
s MONOLITHIC CMOS RECEIVER
s 3.3V SUPPLY VOLTAGE
s LOW-JITTER, ON-CHIP CLOCK RECOVERY
256xFs OUTPUT CLOCK PROVIDED
s SUPPORTS: AES/EBU, IEC 958, S/PDIF, &
EIAJ CP-340/1201 PROFESSIONAL AND
CONSUMER FORMATS
s EXTENSIVE ERROR REPORTING REPEAT
LAST SAMPLE ON ERROR OPTION
DESCRIPTION
The STA120 is a monolithic CMOS device that re-
ceives and decodes audio data according to the
AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201
interface standards.
The STA120 recovers the clock and synchroniza-
BLOCK DIAGRAM
SO28
ORDERING NUMBER: STA120D
tion signals and de-multiplexes the audio and dig-
ital data. Differential or single ended inputs can be
decoded.
The STA120 de-multiplexes the channel, user and
validity data directly to serial output pins with ded-
icated output pins for the most important channel
status bits.
VD+ DGND
78
VA+ FILT AGND MCK
22 20 21 19
RXP
RXN
9
RS422
10 Receiver
MUX
CLOCK & DATA
RECOVERY
DE MUX
MUX
M3 M2 M1 M0
17 18 24 23
AUDIO
SERIAL PORT
REGISTERS
26
SDATA
12
SCK
11
FSYNC
1
C
14
U
28
VREF
13
CS12/FCK
16 6 5 4 3 2 27
SEL C0/E0 Ca/E1 Cb/E2 Cc/F0 Cd/F1 Ce/F2
25
ERF
15
CBL D97AU613A
December 2002
1/15


STMicroelectronics Electronic Components Datasheet

STA120 Datasheet

DIGITAL AUDIO INTERFACE RECEIVER

No Preview Available !

www.DataSheet4U.com
STA120
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VD+, VA+ Power Supply Voltage
VIN Input Voltage ( excluding pins 9, 10)
Tamb Ambient Operating Temperature (power applied)
Tstg Storage Temperature
Value
4
-0.3 to VD+ +0.3
-30 to +85
-40 to 150
Unit
V
V
°C
°C
PIN CONNECTIONS (Top view)
C
Cd/F1
Cc/F0
Cb/E2
Ca/E1
C0/E0
VD+
DGND
RXP
RXN
FSYNC
SCK
CS12/FCK
U
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
D97AU609A
VERF
Ce/F2
SDATA
ERF
M1
M0
VA+
AGND
FILT
MCK
M2
M3
SEL
CBL
PINS DESCRIPTION
N. Name
Description
Power Supply
7 VD+ Positive Digital Power.Positive supply for the digital section. Nominally 3.3V.
8 DGND Digital Ground.Ground for the digital section.
21 AGND Analog Ground.Ground for the analog section. AGND should be connected to same ground as
DGND.
22 VA+ Positive Analog Power.Positive supply for the analog section. Nominally 3.3V.
Audio Output Interface
11
12
17, 18,
23, 24
26
FSYNC
SCK
M2, M3,
M1, M0
SDATA
Frame Sync.Delineates the serial data and may indicate the particular channel, left or right and
may be an input or output. The format is based on M0, M1, M2 and M3 pins.
Serial Clock.Serial clock for SDATA pin which can be configured (via the M0, M1, M2 and M3
pins) as an input or output and can sample data on the rising or falling edge. As an output, SCK
will generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample
must be provided in all normal modes.
Serial Port Mode Selects.Selects the format of Fsync and the sample edge of SCK with respect
to SDATA.
Serial Data. Audio data serial output pin.
2/15


Part Number STA120
Description DIGITAL AUDIO INTERFACE RECEIVER
Maker STMicroelectronics
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STA120 Datasheet PDF





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