Description
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3.1 Arm® Cortex®-M7 with FPU.
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3.2 Memory protection unit.
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Features
- Includes ST state-of-the-art patented technology.
- Core: Arm® 32-bit Cortex®-M7 CPU with DPFPU, ART Accelerator and L1-cache: 16 Kbytes I/D cache, allowing 0-wait state execution from embedded Flash and external memories, up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions.
- Memories.
- Up to 2 Mbytes of Flash memory organized into two banks allowing read-while-write.
- SRAM: 512 Kbytes (including 128 Kbytes of data TCM RAM for criti.
