STM32H7S7A8
Key Features
- 32-bit Arm® Cortex®-M7 CPU with MPU and DP-FPU, L1 cache: 32+32-Kbyte instruction and data cache allowing 0-wait state execution from embedded flash memory and external memories, frequency up to 600 MHz, 1284 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions Memories
- 64 Kbytes of user flash memory that can be used for user code and/or external memory configuration.
- SRAM: total 620 Kbytes (548 Kbytes with optional ECC activated) organized as follows: - 64+64 Kbytes minimum of instruction and data TCM RAM for critical real time instructions - 384 Kbytes AXI SRAM (128 Kbytes with optional remap to TCM RAM fully activated - 4 Kbytes of backup SRAM (available in the lowest-power modes)
- Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, FRAM, SDR/LPSDR SDRAM, NOR/NAND memories
- up to 2x Octo-SPI memory interfaces or 1 octoSPI + 1 hexa-SPI with XiP, with support for serial PSRAM/NAND/NOR, HyperRAM™/ HyperFlash™ frame formats running at up to 200 MHz
- 2x SD/SDIO/MMC interfaces 2x DMA controllers to offload the CPU
- 2 × dual-port DMAs with FIFO and linked listed support
