STM32MP251A Datasheet | STMicroelectronics

Features Includes ST state-of-the-art patented technology. Cores - Up to 64-bit dual-core Arm® Cortex®-A35 - Up to 1.5 GHz - 32-Kbyte I + 32-Kbyte D level 1 cache for each core - 512-Kbyte unified level 2 cache - Arm® NEON™ and Arm® Trust Zone® - 32-bit Arm® Cortex®-M33 with FPU/MPU - Up to 400 MHz - L1 16-Kbyte I / 16-Kbyte D - Arm® Trust Zone® - 32-bit Arm® Cortex®-M0+ in Smart Run domain - Up to 200 MHz (up to 16 MHz in autonomous mode) Memories - External DDR memory up to 4 Gbytes - Up to DDR3L-2133 16/32-bit - Up to DDR4-2400 16/32-bit - Up to LPDDR4-2400 16/32-bit - 808-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video RAM or SYSRAM extension, 256-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with ECC in backup domain, 8-Kbyte SRAM with ECC in backup domain, 32 Kbytes in Smart Run domain - Two Octo-SPI memory interfaces - Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs, and SLC NAND memories with up to 8-bit ECC Security/safety - Trust Zone® peripherals, active tamper, environmental monitors, display secure layers, hardware accelerators - plete resource isolation framework Reset and power management - 1.71 to 1.95 V and 2.7/3.0 to 3.6 V multiple section I/O supply - POR, PDR, PVD, and BOR - On-chip LDO and power-switches for RETRAM, BKPSRAM, VSW, and Smart Run domains - Dedicated supplies for Cortex®-A35 and GPU/NPU (if present) - Internal temperature sensors - Low-power modes: Sleep, Stop, and Standby - DDR memory retention in Standby mode DS14285 - Rev 1 - March 2024 For further information contact your local STMicroelectronics sales office. .st. Prerelease product(s) STM32MP251A/D STM32MP253A/D STM32MP255A/D...