STM8AF51AA
Features
Core
- Max f CPU: 24 MHz
- Advanced STM8A core with Harvard architecture and 3-stage pipeline
- Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz f CPU for industry standard benchmark
LQFP48 7x7
LQFP80 14x14
LQFP64 10x10 LQFP32 7x7
Memories
- munication interfaces
- -
Program memory: 48 to 128 Kbytes Flash; data retention 20 years at 55 °C after 1 kcycle
- Data memory: 1.5 to 2 Kbytes true data EEPROM; endurance 300 kcycles
- RAM: 3 to 6 Kbytes
Clock management
- Low power crystal resonator oscillator with external clock input
- Internal, user-trimmable 16 MHz RC and low power 128 k Hz RC oscillators
- Clock security system with clock monitor
High speed 1 Mbit/s active CAN 2.0B interface USART with clock output for synchronous operation
- LIN master mode
- LINUART LIN 2.1 pliant, master/slave modes with automatic resynchronization
- SPI interface up to 10 Mbit/s or (f CPU/2) 2
- I C interface up to 400 Kbit/s
Analog to digital converter (ADC)
- 10-bit, 3...
