STM8AF6213A
Overview
- AEC-Q100 qualified
- Core - Max fCPU: 16 MHz - Advanced STM8A core with Harvard architecture and 3-stage pipeline - Extended instruction set
- Memories - Program memory: 4 to 8 Kbyte Flash program; data retention 20 years at 55 °C after 1 kcycle - Data memory: 640 byte true data EEPROM; endurance 300 kcycle - RAM: 1 Kbyte
- Clock management - Low-power crystal resonator oscillator with external clock input - Internal, user-trimmable 16 MHz RC and low-power 128 kHz RC oscillators - Clock security system with clock monitor
- Reset and supply management - Wait/auto-wakeup/Halt low-power modes with user definable clock gating - Low-consumption power-on and powerdown reset
- Interrupt management - Nested interrupt controller with 32 interrupts - Up to 28 external interrupts on 7 vectors
- Timers - Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization - 16-bit general purpose timer with 3 CAPCOM channels each (IC, OC, PWM) - 8-bit AR basic timer with 8-bit prescaler - Auto-wakeup timer - Window and independent watchdog timers
