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TDA7521 Datasheet

Analog Front End

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TDA7521
Analog Front End
PRODUCT PREVIEW
TDA7521 is a BiCMOS analog front end for CD appli-
cations. Four input signals (AC*, BD*, E* and F*),
coming from the pick-up (whose laser diode is driven
and controlled by the device itself), are preamplified
by a programmable voltage-to-voltage or current-to-
voltage stage, depending on the used pick-up. The
output signals from the preamplifier stage (AC, BD, E,
F and HF, a radio frequency signal obtained by com-
bining the photo-detector outputs as A+B+C+D) are
fed to an 8-bit HF ADC (for HF, which carries encoded
audio data) and a 6-bit Servo ADC (for AC, BD, E and
F, used for focusing, tracking the laser beam and con-
trolling revolution speed). All these signals are digi-
tized, multiplexed, synchronized with the external
clock (768×Fs or 394×Fs, Fs=44.1KHz) and fed to the
digital counterpart in one only digital stream (AC/HF/
BD/HF/E/HF/F/HF). Two stereo DACs convert the in-
put bitstreams from TDA7522.
TQFP44
(10 x 10 x 1.40 mm body)
All the clock signals (for ADCs and DACs) are generated by a low-jitter PLL-based clock manager. All
TDA7521’s analog preprocessing is controlled by TDA7522 by means of an UART interface (which imple-
ments an I2C-like protocol). Housed in a TQFP 44, 10×10mm package, TDA7521 features the functions
shown in figure below.
TDA7521 uses the HF4CMOS technology and is supplied @5Vdc.
May 1998
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/11


STMicroelectronics Electronic Components Datasheet

TDA7521 Datasheet

Analog Front End

No Preview Available !

TDA7521
Figure 1. TDA7521 Block Diagram
REF IN
PON
AC
BD
E
F
REXT REF OUT
REF
Gen
I/V
I/V
I/V
I/V
Control I/F
SDA SCL
HF MON
FILT
CLOCK
Mgr
RF
ADC
Servo
ADC
Output MUX
Laser
Driver
LD MD
Stereo
DAC
MUTEL MUTER DL DR
CKIN
SYNC
d0
d1
d2
d3
d4
d5
d6/OF
d7/UF
OUTL
OUTR
1.0 HARDWARE DESCRIPTION
1.1 Clock source and generation
The master clock to operate the device is 768×Fs (High Frequency mode, HFM) or 384×Fs (Low Frequen-
cy mode, LFM). Fs=44.1KHz for CD applications. In either case, the clock is generated by TDA7522: an
internal low-jitter Charge-Pump PLL (CPPLL) and a Finite State Machine (FSM) synthesize all the needed
clocks for the internal blocks: a 512×Fs for the DAC and three 384×Fs (HFM) or 192×Fs (LFM), with dif-
ferent phases for ADCs and output digital multiplexer. The required loop filter network is made up of a
160pF capacitor from FILT to GND_pll in parallel with the series of a 10nF and a 4Kresistor. All clock-
related setups are communicated to TDA7521 via UART interface.
1.2 Voltage references
REFIN is an internal voltage reference generated by a resistor divider between VCC_dac and VSS_dac.
Nominal value (with VCC_dac=5V) is REFIN=2.5V. Careful filtering of this pin is essential; recommended
value of external capacitor is 47µF paralleled with 100nF ceramic. REFOUT is a 2.5V (nominal) buffered
output to bias the pickup. All the internal voltage references for ADCs and DACs are generated by band-
gap-based circuits, thus allowing to reduce the noise induced by the power supply.
2/11


Part Number TDA7521
Description Analog Front End
Maker ST Microelectronics
Total Page 11 Pages
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