UPSD3422
Description
22 3 Hardware description.
Key Features
- Advanced core, 4-clocks per instruction
- Clock, reset, and power supply management le u – Flexible 8-level CPU clock divider register so rod – Normal, Idle, and power-down modes
- Programmable logic, general purpose
- Packages – ECOPACK® pliant
- Device summary
- A/D converter – Eight channels, 10-bit resolution, 6 µs
- Operating voltage source (±10%) – 5 V devices: 5.0 V and 3.3 V sources
