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CD4034BMS Datasheet Preview

CD4034BMS Datasheet

CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register

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CD4034
CMOS 8-Stage Static Bidirectional Parallel/Serial
Input/Output Bus Register
Features
Description
• High Voltage Types (20V Rating)
• Bidirectional Parallel Data Input
• Parallel or Serial Inputs/Parallel Outputs
• Asynchronous or Synchronous Parallel Data Loading
• Parallel Data-Input Enable on “A” Data Lines (3-State
Output)
• Data Recirculation for Register Expansion
• Multipackage Register Expansion
• Fully Static Operation DC-to-10MHz (typ.) at
VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Parallel Input/Parallel Output, Serial Input/Parallel Out-
put, Serial Input/Serial Output Register
• Shift Right/Shift Left Register
• Shift Right/Shift Left With Parallel Loading
• Address Register
• Buffer Register
• Bus System Register with Enable Parallel Lines at Bus
Side
• Double Bus Register System
• Up-Down Johnson or Ring Counter
• Pseudo-Random Code Generators
• Sample and Hold Register (Storage, Counting,
Display)
• Frequency and Phase Comparator
CD4034BMS is a static eight-stage parallel-or serial-input
parallel-output register. It can be used to:
1) bidirectionally transfer parallel information between two
buses, 2) convert serial data to parallel form and direct the
parallel data to either of two buses, 3) store (recirculate) par-
allel data, or 4) accept parallel data from either of two buses
and convert that data to serial form. Inputs that control the
operations include a single-phase CLOCK (CL), A DATA
ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S),
A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARAL-
LEL/SERIAL (P/S).
Data inputs include 16 bidirectional parallel data lines of
which the eight A data lines are inputs (3-state outputs) and
the B data lines are outputs (inputs) depending on the signal
level on the A/B input. In addition, an input for SERIAL DATA
is also provided.
All register stages are D-type master-slave flip-flops with
separate master and slave clock inputs generated internally
to allow synchronous or asynchronous data transfer from
master to slave. Isolation from external noise and the effects
of loading is provided by output buffering.
Pinout
CD4034BMS
TOP VIEW
81
72
63
54
45
36
27
18
“A” ENABLE 9
SERIAL INPUT 10
A/B 11
VSS 12
24 VDD
23 8
22 7
21 6
20 5
19 4
18 3
17 2
16 1
15 CLOCK
14 A/S
13 P/S
www.sycelectronica.com.ar




SYC

CD4034BMS Datasheet Preview

CD4034BMS Datasheet

CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register

No Preview Available !

CD4034BMS
Parallel Operation
Functional Diagram
A high P/S input signal allows data transfer into the register
via the parallel data lines synchronously with the positive
transition of the clock provided the A/S input is low. If the A/S
input is high the transfer is independent of the clock. The
direction of data flow is controlled by the A/B input. When
this signal is high the A data lines are inputs (and B data
lines are outputs); a low A/B signal reverses the direction of
data flow.
SI
AE
A/B
STEERING
LOGIC
A/S
P/S
CL
The AE input is an additional feature which allows many reg-
isters to feed data to a common bus. The A DATA lines are
enabled only when this signal is high.
Data storage through recirculation of data in each register
stage is accomplished by making the A/B signal high and the
AE signal low.
Serial Operation
SI
A1 Q
B1
SI
6
STAGES
A low P/S signal allows serial data to transfer into the regis-
ter synchronously with the positive transition of the clock.
The A/S input is internally disabled when the register is in
the serial mode (asynchronous serial operation is not
allowed).
Q
SI
A8 B8
The serial data appears as output data on either the B lines
(when A/B is high) or the A lines (when A/B is low and the
AE signal is high).
Register expansion can be accomplished by simply cascad-
ing CD4034BMS packages.
The CD4034BMS is supplied in these 24 lead outline pack-
ages:
Braze Seal DIP H4V
Ceramic Flatpack H4P
www.sycelectronica.com.ar


Part Number CD4034BMS
Description CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register
Maker SYC
Total Page 14 Pages
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