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S T U/D421S
S amHop Microelectronics C orp.
Aug.20,2006
P -C hannel Logic Level E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
V DS S
-40V
F E AT UR E S
( m W ) Max
ID
-10A
R DS (ON)
S uper high dense cell design for low R DS (ON ).
45 @ V G S = -10V 60 @ V G S = -4.5V
R ugged and reliable. TO-252 and TO-251 P ackage.
D
D G S
G D
S
G
S TU S E R IE S TO-252AA(D-P AK)
S TD S E R IE S TO-251(l-P AK)
S
AB S OL UTE MAXIMUM R ATINGS
P arameter Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous @ Ta -P ulsed
b a
(T A =25 C unles s otherwis e noted)
S ymbol V DS V GS Limit -40 20 -10 -8.
STD421S Datasheet
