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K4S643232H-UC-L55 Datasheet 2M x 32 SDRAM

Manufacturer: Samsung Semiconductor

Overview: K4S643232H SDRAM 2M x 32 SDRAM 86 TSOP-II with Pb-Free (RoHS compliant) Revision 1.2 April 2006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.2 April 2006 K4S643232H Revision History Revision 0.0 0.1 1.1 1.2 Month October November August April Year 2003 2003 2004 2006 - Preliminary spec First release. - Final spec release. - Corrected typo. - Applied now format and corrected typo. History SDRAM - 2 - Rev. 1.

Download the K4S643232H-UC-L55 datasheet PDF. This datasheet also includes the K4S643232H-UC-L70 variant, as both parts are published together in a single manufacturer document.

General Description

The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32

Key Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM (x4,x8) & L(U)DQM (x16) for masking.
  • Auto & self refresh.
  • 15.6u.