K4T56083QF Datasheet | Samsung Semiconductor

Feature 2. Package Pinout/Mechnical Dimension & Addressing 2.1 Package Pintout & Mechnical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & Specifications Page 2 of 27 Rev. 1.5 Feb. 2005 256Mb F-die DDR2 SDRAM 0. Ordering Information Organization 64Mx4 64Mx4 32Mx8 32Mx8 DDR2-667 5-5-5 K4T56083QF-GCE6 K4T56083QF-ZCE6 DDR2-533 4-4-4 K4T56043QF-GCD5 K4T56043QF-ZCD5 K4T56083QF-GCD5 K4T56083QF-ZCD5 DDR2-400 3-3-3 K4T56043QF-GCCC K4T56043QF-ZCCC K4T56083QF-GCCC K4T56083QF-ZCCC DDR2 SDRAM Package Leaded Lead-free Leaded Lead-free Note: Speed bin is in order of CL-t RCD-t RP 1.Key Features Speed CAS Latency t RCD(min) t RP(min) t RC(min) DDR2-667 5-5-5 5 15 15 54 DDR2-533 4-4-4 4 15 15 55 DDR2-400 3-3-3 3 15 15 55 Units t CK ns ns ns - JEDEC standard 1.8V ± 0.1V Power Supply - VDDQ = 1.8V ± 0.1V - 200 MHz f CK for 400Mb/sec/pin, 267MHz f CK for 533Mb/sec/pin, 333MHz f CK for 667Mb/sec/pin - 4 Banks - Posted CAS - Programmable CAS Latency: 3, 4, 5 - Programmable Additive Latency: 0, 1 , 2 , 3 and 4 - Write Latency(WL) = Read Latency(RL) -1 - Burst Length: 4 , 8(Interleave/nibble sequential) - Programmable Sequential / Interleave Burst Mode - Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature ) - Off-Chip Driver(OCD) Impedance Adjustment - On Die Termination - Average Refesh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C - Package: 60ball FBGA - 64Mx4/32Mx8 - All of Lead-free products are pliant for Ro HS The 256Mb DDR2 SDRAM chip is organized as either 16Mbit x 4 I/Os x 4 banks or 8Mbit x 8 I/Os x 4banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 667Mb/sec/pin (DDR2667) for general applications. The chip is designed to ply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die...