are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog f.

Table 1-1. S3C831B Pin Descriptions Pin Names P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0-P1.3 Pin Type I/O Pin Description I/O port with bit programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups..

S3C830A

S3C8075

S3C8095

S3C80A4

S3C80A5

S3C80A8

S3C80B4

S3C80B5

S3C80B8

S3C80E5

S3C80E7

S3C80F7

S3C80F9